[llvm] [RISCV][NFC] Convert some predicates to TIIPredicate (PR #129658)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 22 09:05:58 PDT 2025
================
@@ -0,0 +1,143 @@
+//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instruction predicates.
+//
+//===----------------------------------------------------------------------===//
+
+// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
+def isSEXT_W
+ : TIIPredicate<"isSEXT_W",
+ MCReturnStatement<CheckAll<[
+ CheckOpcode<[ADDIW]>,
+ CheckIsRegOperand<1>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 0>
+ ]>>>;
+
+// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
+def isZEXT_W
+ : TIIPredicate<"isZEXT_W",
+ MCReturnStatement<CheckAll<[
+ CheckOpcode<[ADD_UW]>,
+ CheckIsRegOperand<1>,
+ CheckIsRegOperand<2>,
+ CheckRegOperand<2, X0>
+ ]>>>;
+
+// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
+def isZEXT_B
+ : TIIPredicate<"isZEXT_B",
+ MCReturnStatement<CheckAll<[
+ CheckOpcode<[ANDI]>,
+ CheckIsRegOperand<1>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 255>
+ ]>>>;
+
+// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
+def isSelectPseudo
+ : TIIPredicate<"isSelectPseudo",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
----------------
topperc wrote:
Why can't this use `CheckOpcode`?
https://github.com/llvm/llvm-project/pull/129658
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