[llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)

[Gheorghe-Teodor Bercea via llvm-commits]

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@@ -344,9 +344,10 @@ unsigned GCNTTIImpl::getMinVectorRegisterBitWidth() const {
 unsigned GCNTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
   if (Opcode == Instruction::Load || Opcode == Instruction::Store)
     return 32 * 4 / ElemWidth;
-  return (ElemWidth == 16 && ST->has16BitInsts()) ? 2
-       : (ElemWidth == 32 && ST->hasPackedFP32Ops()) ? 2
-       : 1;
+  return ElemWidth == 8                                ? 4
+         : (ElemWidth == 16 && ST->has16BitInsts())    ? 2
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doru1004 wrote:

I would like to keep this patch about i8s only. If we want to relax conditions for other types it can be done in a separate PR.

https://github.com/llvm/llvm-project/pull/134934