[llvm] [RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (PR #136824)

[Jim Lin via llvm-commits]

================
@@ -2016,6 +2026,37 @@ foreach vtiToWti = AllWidenableIntVectors in {
   }
 }
 
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjointVL_VV_VX<SDNode extop, string instruction_name> {
+  foreach vtiToWti = AllWidenableIntVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<wti>.Predicates) in {
+      def : Pat<(wti.Vector (extop (vti.Vector
+                                     (riscv_or_vl_is_add_oneuse
+                                       vti.RegClass:$rs2, vti.RegClass:$rs1,
+                                       undef, srcvalue, srcvalue)),
+                                    VMV0:$vm, VLOpFrag)),
+                (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
+                   (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+                   vti.RegClass:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
----------------
tclin914 wrote:

```suggestion
                (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
                 (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
                 vti.RegClass:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
```

https://github.com/llvm/llvm-project/pull/136824