[llvm] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)

[Shilei Tian via llvm-commits]

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/135820

>From 52f0431e9b268bb96956d8b9bae9effcbb1c791b Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Mon, 21 Apr 2025 13:48:31 -0400
Subject: [PATCH] [AMDGPU][Verifier] Check address space of `alloca`
 instruction

---
 llvm/lib/IR/Verifier.cpp                      |  6 ++++
 .../AMDGPU/lower-indirect-lds-references.ll   |  5 +--
 llvm/test/Verifier/AMDGPU/alloca.ll           | 36 +++++++++++++++++++
 3 files changed, 45 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/Verifier/AMDGPU/alloca.ll

diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 8afe360d088bc..78d259745244f 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -4392,6 +4392,12 @@ void Verifier::visitAllocaInst(AllocaInst &AI) {
     verifySwiftErrorValue(&AI);
   }
 
+  if (TT.isAMDGPU()) {
+    Check(AI.getAddressSpace() == DL.getAllocaAddrSpace() ||
+              AI.getAddressSpace() == 0,
+          "alloca on amdgpu must be in addrspace(0) or addrspace(5)", &AI);
+  }
+
   visitInstruction(AI);
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll b/llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
index 1b0c8d66d3ebc..4309dacc9da2b 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
@@ -16,8 +16,9 @@ define amdgpu_kernel void @offloading_kernel() {
 }
 
 define void @call_unknown() {
-  %1 = alloca ptr, align 8
-  %2 = call i32 %1()
+  %alloca = alloca ptr, align 8, addrspace(5)
+  %alloca.cast = addrspacecast ptr addrspace(5) %alloca to ptr
+  %ret = call i32 %alloca.cast()
   ret void
 }
 
diff --git a/llvm/test/Verifier/AMDGPU/alloca.ll b/llvm/test/Verifier/AMDGPU/alloca.ll
new file mode 100644
index 0000000000000..09b251bf860e1
--- /dev/null
+++ b/llvm/test/Verifier/AMDGPU/alloca.ll
@@ -0,0 +1,36 @@
+; RUN: not llvm-as %s --disable-output 2>&1 | FileCheck %s
+
+target triple = "amdgcn-amd-amdhsa"
+
+target datalayout = "A5"
+
+; CHECK: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.1 = alloca i32, align 4, addrspace(1)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.2 = alloca i32, align 4, addrspace(2)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.3 = alloca i32, align 4, addrspace(3)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.4 = alloca i32, align 4, addrspace(4)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.6 = alloca i32, align 4, addrspace(6)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.7 = alloca i32, align 4, addrspace(7)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.8 = alloca i32, align 4, addrspace(8)
+; CHECK-NEXT: alloca on amdgpu must be in addrspace(0) or addrspace(5)
+; CHECK-NEXT: %alloca.9 = alloca i32, align 4, addrspace(9)
+define void @foo() {
+entry:
+  %alloca.0 = alloca i32, align 4
+  %alloca.1 = alloca i32, align 4, addrspace(1)
+  %alloca.2 = alloca i32, align 4, addrspace(2)
+  %alloca.3 = alloca i32, align 4, addrspace(3)
+  %alloca.4 = alloca i32, align 4, addrspace(4)
+  %alloca.5 = alloca i32, align 4, addrspace(5)
+  %alloca.6 = alloca i32, align 4, addrspace(6)
+  %alloca.7 = alloca i32, align 4, addrspace(7)
+  %alloca.8 = alloca i32, align 4, addrspace(8)
+  %alloca.9 = alloca i32, align 4, addrspace(9)
+  ret void
+}