[llvm] 41f7a85 - [SPARC] Promote i32 CTTZ when we have VIS3
via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 26 08:16:24 PDT 2025
Author: Koakuma
Date: 2025-04-26T22:16:21+07:00
New Revision: 41f7a85317f4f345895395697f9129b10f1802b3
URL: https://github.com/llvm/llvm-project/commit/41f7a85317f4f345895395697f9129b10f1802b3
DIFF: https://github.com/llvm/llvm-project/commit/41f7a85317f4f345895395697f9129b10f1802b3.diff
LOG: [SPARC] Promote i32 CTTZ when we have VIS3
CTTZ can be implemented in terms of CTLZ, for which there's a native
instruction in VIS3.
Promote i32 CTTZ in that case so that the native instruction gets used.
Reviewers: rorth, brad0, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/135894
Added:
Modified:
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/Sparc/SparcISelLowering.h
llvm/test/CodeGen/SPARC/cttz.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 0bfa202c9f92e..0b98327d53434 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1757,7 +1757,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, MVT::i64,
Subtarget->usePopc() ? Legal : Expand);
- setOperationAction(ISD::CTTZ, MVT::i64, Expand);
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
setOperationAction(ISD::ROTL , MVT::i64, Expand);
setOperationAction(ISD::ROTR , MVT::i64, Expand);
@@ -1817,8 +1816,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
- setOperationAction(ISD::FMA , MVT::f32, Expand);
- setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
setOperationAction(ISD::ROTL , MVT::i32, Expand);
setOperationAction(ISD::ROTR , MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
@@ -1996,17 +1994,36 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
+
+ setOperationAction(ISD::CTTZ, MVT::i32,
+ Subtarget->is64Bit() ? Promote : Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32,
+ Subtarget->is64Bit() ? Promote : Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
} else if (Subtarget->usePopc()) {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
+
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
} else {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32,
Subtarget->is64Bit() ? Promote : LibCall);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, LibCall);
+
+ // FIXME here we don't have any ISA extensions that could help us, so to
+ // prevent large expansions those should be made into LibCalls.
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
}
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@@ -3596,6 +3613,15 @@ bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
+bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
+ // We lack native cttz, however,
+ // On 64-bit targets it is cheap to implement it in terms of popc.
+ if (Subtarget->is64Bit() && Subtarget->usePopc())
+ return true;
+ // Otherwise, implementing cttz in terms of ctlz is still cheap.
+ return isCheapToSpeculateCtlz(Ty);
+}
+
// Override to disable global variable loading on Linux.
void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
if (!Subtarget->isTargetLinux())
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index ef87e20094c98..deb66854a1e7a 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -216,6 +216,8 @@ namespace llvm {
return isCtlzFast();
}
+ bool isCheapToSpeculateCttz(Type *Ty) const override;
+
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
// FIXME: We insert fences for each atomics and generate
// sub-optimal code for PSO/TSO. (Approximately nobody uses any
diff --git a/llvm/test/CodeGen/SPARC/cttz.ll b/llvm/test/CodeGen/SPARC/cttz.ll
index eab2433a074a2..05c47b868c830 100644
--- a/llvm/test/CodeGen/SPARC/cttz.ll
+++ b/llvm/test/CodeGen/SPARC/cttz.ll
@@ -1,70 +1,436 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=sparc -mcpu=v9 | FileCheck %s
+; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC
+; RUN: llc < %s -mtriple=sparc -mattr=popc | FileCheck %s -check-prefix=SPARC-POPC
+; RUN: llc < %s -mtriple=sparc -mattr=vis3 | FileCheck %s -check-prefix=SPARC-VIS3
+; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=SPARC64
+; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=SPARC64-POPC
+; RUN: llc < %s -mtriple=sparcv9 -mattr=vis3 | FileCheck %s -check-prefix=SPARC64-VIS3
-define i32 @f(i32 %x) {
-; CHECK-LABEL: f:
-; CHECK: .cfi_startproc
-; CHECK-NEXT: ! %bb.0: ! %entry
-; CHECK-NEXT: sub %g0, %o0, %o1
-; CHECK-NEXT: and %o0, %o1, %o1
-; CHECK-NEXT: sethi 122669, %o2
-; CHECK-NEXT: or %o2, 305, %o2
-; CHECK-NEXT: smul %o1, %o2, %o1
-; CHECK-NEXT: srl %o1, 27, %o1
-; CHECK-NEXT: sethi %hi(.LCPI0_0), %o2
-; CHECK-NEXT: add %o2, %lo(.LCPI0_0), %o2
-; CHECK-NEXT: ldub [%o2+%o1], %o1
-; CHECK-NEXT: cmp %o0, 0
-; CHECK-NEXT: move %icc, 0, %o1
-; CHECK-NEXT: retl
-; CHECK-NEXT: mov %o1, %o0
-entry:
- %0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
- %1 = icmp eq i32 %x, 0
- %2 = select i1 %1, i32 0, i32 %0
- %3 = trunc i32 %2 to i8
- %conv = zext i8 %3 to i32
- ret i32 %conv
+define i32 @i32_nopoison(i32 %x) nounwind {
+; SPARC-LABEL: i32_nopoison:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: cmp %o0, 0
+; SPARC-NEXT: be .LBB0_2
+; SPARC-NEXT: nop
+; SPARC-NEXT: ! %bb.1: ! %cond.false
+; SPARC-NEXT: sub %g0, %o0, %o1
+; SPARC-NEXT: and %o0, %o1, %o0
+; SPARC-NEXT: sethi 122669, %o1
+; SPARC-NEXT: or %o1, 305, %o1
+; SPARC-NEXT: smul %o0, %o1, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: sethi %hi(.LCPI0_0), %o1
+; SPARC-NEXT: add %o1, %lo(.LCPI0_0), %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: ldub [%o1+%o0], %o0
+; SPARC-NEXT: .LBB0_2:
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov 32, %o0
+;
+; SPARC-POPC-LABEL: i32_nopoison:
+; SPARC-POPC: ! %bb.0:
+; SPARC-POPC-NEXT: cmp %o0, 0
+; SPARC-POPC-NEXT: be .LBB0_2
+; SPARC-POPC-NEXT: nop
+; SPARC-POPC-NEXT: ! %bb.1: ! %cond.false
+; SPARC-POPC-NEXT: sub %g0, %o0, %o1
+; SPARC-POPC-NEXT: and %o0, %o1, %o0
+; SPARC-POPC-NEXT: sethi 122669, %o1
+; SPARC-POPC-NEXT: or %o1, 305, %o1
+; SPARC-POPC-NEXT: smul %o0, %o1, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: sethi %hi(.LCPI0_0), %o1
+; SPARC-POPC-NEXT: add %o1, %lo(.LCPI0_0), %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: ldub [%o1+%o0], %o0
+; SPARC-POPC-NEXT: .LBB0_2:
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: mov 32, %o0
+;
+; SPARC-VIS3-LABEL: i32_nopoison:
+; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: add %o0, -1, %o1
+; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: mov 32, %o1
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: sub %o1, %o0, %o0
+;
+; SPARC64-LABEL: i32_nopoison:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: cmp %o0, 0
+; SPARC64-NEXT: be %icc, .LBB0_2
+; SPARC64-NEXT: nop
+; SPARC64-NEXT: ! %bb.1: ! %cond.false
+; SPARC64-NEXT: sub %g0, %o0, %o1
+; SPARC64-NEXT: and %o0, %o1, %o0
+; SPARC64-NEXT: sethi 122669, %o1
+; SPARC64-NEXT: or %o1, 305, %o1
+; SPARC64-NEXT: mulx %o0, %o1, %o0
+; SPARC64-NEXT: srl %o0, 27, %o0
+; SPARC64-NEXT: srl %o0, 0, %o0
+; SPARC64-NEXT: sethi %h44(.LCPI0_0), %o1
+; SPARC64-NEXT: add %o1, %m44(.LCPI0_0), %o1
+; SPARC64-NEXT: sllx %o1, 12, %o1
+; SPARC64-NEXT: add %o1, %l44(.LCPI0_0), %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: ldub [%o1+%o0], %o0
+; SPARC64-NEXT: .LBB0_2:
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: mov 32, %o0
+;
+; SPARC64-POPC-LABEL: i32_nopoison:
+; SPARC64-POPC: ! %bb.0:
+; SPARC64-POPC-NEXT: add %o0, -1, %o1
+; SPARC64-POPC-NEXT: andn %o1, %o0, %o0
+; SPARC64-POPC-NEXT: srl %o0, 0, %o0
+; SPARC64-POPC-NEXT: retl
+; SPARC64-POPC-NEXT: popc %o0, %o0
+;
+; SPARC64-VIS3-LABEL: i32_nopoison:
+; SPARC64-VIS3: ! %bb.0:
+; SPARC64-VIS3-NEXT: sethi 0, %o1
+; SPARC64-VIS3-NEXT: or %o1, 0, %o2
+; SPARC64-VIS3-NEXT: or %o1, 1, %o1
+; SPARC64-VIS3-NEXT: sllx %o1, 32, %o1
+; SPARC64-VIS3-NEXT: or %o1, %o2, %o1
+; SPARC64-VIS3-NEXT: or %o0, %o1, %o0
+; SPARC64-VIS3-NEXT: add %o0, -1, %o1
+; SPARC64-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC64-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC64-VIS3-NEXT: mov 64, %o1
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: sub %o1, %o0, %o0
+ %ret = call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ ret i32 %ret
}
-define i64 @g(i64 %x) {
-; CHECK-LABEL: g:
-; CHECK: .cfi_startproc
-; CHECK-NEXT: ! %bb.0: ! %entry
-; CHECK-NEXT: sub %g0, %o1, %o2
-; CHECK-NEXT: and %o1, %o2, %o2
-; CHECK-NEXT: sethi 122669, %o3
-; CHECK-NEXT: or %o3, 305, %o3
-; CHECK-NEXT: smul %o2, %o3, %o2
-; CHECK-NEXT: sethi %hi(.LCPI1_0), %o4
-; CHECK-NEXT: add %o4, %lo(.LCPI1_0), %o4
-; CHECK-NEXT: sub %g0, %o0, %o5
-; CHECK-NEXT: and %o0, %o5, %o5
-; CHECK-NEXT: smul %o5, %o3, %o3
-; CHECK-NEXT: srl %o3, 27, %o3
-; CHECK-NEXT: ldub [%o4+%o3], %o3
-; CHECK-NEXT: srl %o2, 27, %o2
-; CHECK-NEXT: ldub [%o4+%o2], %o4
-; CHECK-NEXT: add %o3, 32, %o2
-; CHECK-NEXT: cmp %o1, 0
-; CHECK-NEXT: movne %icc, %o4, %o2
-; CHECK-NEXT: or %o1, %o0, %o0
-; CHECK-NEXT: cmp %o0, 0
-; CHECK-NEXT: move %icc, 0, %o2
-; CHECK-NEXT: mov %g0, %o0
-; CHECK-NEXT: retl
-; CHECK-NEXT: mov %o2, %o1
-entry:
- %0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
- %1 = icmp eq i64 %x, 0
- %2 = select i1 %1, i64 0, i64 %0
- %3 = trunc i64 %2 to i32
- %conv = zext i32 %3 to i64
- ret i64 %conv
+define i32 @i32_poison(i32 %x) nounwind {
+; SPARC-LABEL: i32_poison:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: sub %g0, %o0, %o1
+; SPARC-NEXT: and %o0, %o1, %o0
+; SPARC-NEXT: sethi 122669, %o1
+; SPARC-NEXT: or %o1, 305, %o1
+; SPARC-NEXT: smul %o0, %o1, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: sethi %hi(.LCPI1_0), %o1
+; SPARC-NEXT: add %o1, %lo(.LCPI1_0), %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: ldub [%o1+%o0], %o0
+;
+; SPARC-POPC-LABEL: i32_poison:
+; SPARC-POPC: ! %bb.0:
+; SPARC-POPC-NEXT: sub %g0, %o0, %o1
+; SPARC-POPC-NEXT: and %o0, %o1, %o0
+; SPARC-POPC-NEXT: sethi 122669, %o1
+; SPARC-POPC-NEXT: or %o1, 305, %o1
+; SPARC-POPC-NEXT: smul %o0, %o1, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: sethi %hi(.LCPI1_0), %o1
+; SPARC-POPC-NEXT: add %o1, %lo(.LCPI1_0), %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: ldub [%o1+%o0], %o0
+;
+; SPARC-VIS3-LABEL: i32_poison:
+; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: add %o0, -1, %o1
+; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: mov 32, %o1
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: sub %o1, %o0, %o0
+;
+; SPARC64-LABEL: i32_poison:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: sub %g0, %o0, %o1
+; SPARC64-NEXT: and %o0, %o1, %o0
+; SPARC64-NEXT: sethi 122669, %o1
+; SPARC64-NEXT: or %o1, 305, %o1
+; SPARC64-NEXT: mulx %o0, %o1, %o0
+; SPARC64-NEXT: srl %o0, 27, %o0
+; SPARC64-NEXT: srl %o0, 0, %o0
+; SPARC64-NEXT: sethi %h44(.LCPI1_0), %o1
+; SPARC64-NEXT: add %o1, %m44(.LCPI1_0), %o1
+; SPARC64-NEXT: sllx %o1, 12, %o1
+; SPARC64-NEXT: add %o1, %l44(.LCPI1_0), %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: ldub [%o1+%o0], %o0
+;
+; SPARC64-POPC-LABEL: i32_poison:
+; SPARC64-POPC: ! %bb.0:
+; SPARC64-POPC-NEXT: add %o0, -1, %o1
+; SPARC64-POPC-NEXT: andn %o1, %o0, %o0
+; SPARC64-POPC-NEXT: srl %o0, 0, %o0
+; SPARC64-POPC-NEXT: retl
+; SPARC64-POPC-NEXT: popc %o0, %o0
+;
+; SPARC64-VIS3-LABEL: i32_poison:
+; SPARC64-VIS3: ! %bb.0:
+; SPARC64-VIS3-NEXT: add %o0, -1, %o1
+; SPARC64-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC64-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC64-VIS3-NEXT: mov 64, %o1
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: sub %o1, %o0, %o0
+ %ret = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ ret i32 %ret
}
-; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
-declare i32 @llvm.cttz.i32(i32, i1 immarg) #0
-declare i64 @llvm.cttz.i64(i64, i1 immarg) #0
+define i64 @i64_nopoison(i64 %x) nounwind {
+; SPARC-LABEL: i64_nopoison:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: sethi 122669, %o2
+; SPARC-NEXT: or %o2, 305, %o2
+; SPARC-NEXT: sethi %hi(.LCPI2_0), %o3
+; SPARC-NEXT: cmp %o0, 0
+; SPARC-NEXT: be .LBB2_3
+; SPARC-NEXT: add %o3, %lo(.LCPI2_0), %o3
+; SPARC-NEXT: ! %bb.1:
+; SPARC-NEXT: sub %g0, %o0, %o4
+; SPARC-NEXT: and %o0, %o4, %o0
+; SPARC-NEXT: smul %o0, %o2, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: cmp %o1, 0
+; SPARC-NEXT: be .LBB2_4
+; SPARC-NEXT: ldub [%o3+%o0], %o0
+; SPARC-NEXT: .LBB2_2:
+; SPARC-NEXT: sub %g0, %o1, %o0
+; SPARC-NEXT: and %o1, %o0, %o0
+; SPARC-NEXT: smul %o0, %o2, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: ldub [%o3+%o0], %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov %g0, %o0
+; SPARC-NEXT: .LBB2_3:
+; SPARC-NEXT: mov 32, %o0
+; SPARC-NEXT: cmp %o1, 0
+; SPARC-NEXT: bne .LBB2_2
+; SPARC-NEXT: nop
+; SPARC-NEXT: .LBB2_4:
+; SPARC-NEXT: add %o0, 32, %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov %g0, %o0
+;
+; SPARC-POPC-LABEL: i64_nopoison:
+; SPARC-POPC: ! %bb.0:
+; SPARC-POPC-NEXT: sethi 122669, %o2
+; SPARC-POPC-NEXT: or %o2, 305, %o2
+; SPARC-POPC-NEXT: sethi %hi(.LCPI2_0), %o3
+; SPARC-POPC-NEXT: cmp %o0, 0
+; SPARC-POPC-NEXT: be .LBB2_3
+; SPARC-POPC-NEXT: add %o3, %lo(.LCPI2_0), %o3
+; SPARC-POPC-NEXT: ! %bb.1:
+; SPARC-POPC-NEXT: sub %g0, %o0, %o4
+; SPARC-POPC-NEXT: and %o0, %o4, %o0
+; SPARC-POPC-NEXT: smul %o0, %o2, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: cmp %o1, 0
+; SPARC-POPC-NEXT: be .LBB2_4
+; SPARC-POPC-NEXT: ldub [%o3+%o0], %o0
+; SPARC-POPC-NEXT: .LBB2_2:
+; SPARC-POPC-NEXT: sub %g0, %o1, %o0
+; SPARC-POPC-NEXT: and %o1, %o0, %o0
+; SPARC-POPC-NEXT: smul %o0, %o2, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: ldub [%o3+%o0], %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: mov %g0, %o0
+; SPARC-POPC-NEXT: .LBB2_3:
+; SPARC-POPC-NEXT: mov 32, %o0
+; SPARC-POPC-NEXT: cmp %o1, 0
+; SPARC-POPC-NEXT: bne .LBB2_2
+; SPARC-POPC-NEXT: nop
+; SPARC-POPC-NEXT: .LBB2_4:
+; SPARC-POPC-NEXT: add %o0, 32, %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: mov %g0, %o0
+;
+; SPARC-VIS3-LABEL: i64_nopoison:
+; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: cmp %o1, 0
+; SPARC-VIS3-NEXT: bne .LBB2_2
+; SPARC-VIS3-NEXT: nop
+; SPARC-VIS3-NEXT: ! %bb.1:
+; SPARC-VIS3-NEXT: add %o0, -1, %o1
+; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: ba .LBB2_3
+; SPARC-VIS3-NEXT: mov 64, %o1
+; SPARC-VIS3-NEXT: .LBB2_2:
+; SPARC-VIS3-NEXT: add %o1, -1, %o0
+; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: mov 32, %o1
+; SPARC-VIS3-NEXT: .LBB2_3:
+; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov %g0, %o0
+;
+; SPARC64-LABEL: i64_nopoison:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: brz %o0, .LBB2_2
+; SPARC64-NEXT: nop
+; SPARC64-NEXT: ! %bb.1: ! %cond.false
+; SPARC64-NEXT: sub %g0, %o0, %o1
+; SPARC64-NEXT: and %o0, %o1, %o0
+; SPARC64-NEXT: sethi 3362647, %o1
+; SPARC64-NEXT: or %o1, 447, %o1
+; SPARC64-NEXT: sethi 34344, %o2
+; SPARC64-NEXT: or %o2, 914, %o2
+; SPARC64-NEXT: sllx %o2, 32, %o2
+; SPARC64-NEXT: or %o2, %o1, %o1
+; SPARC64-NEXT: mulx %o0, %o1, %o0
+; SPARC64-NEXT: srlx %o0, 58, %o0
+; SPARC64-NEXT: sethi %h44(.LCPI2_0), %o1
+; SPARC64-NEXT: add %o1, %m44(.LCPI2_0), %o1
+; SPARC64-NEXT: sllx %o1, 12, %o1
+; SPARC64-NEXT: add %o1, %l44(.LCPI2_0), %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: ldub [%o1+%o0], %o0
+; SPARC64-NEXT: .LBB2_2:
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: mov 64, %o0
+;
+; SPARC64-POPC-LABEL: i64_nopoison:
+; SPARC64-POPC: ! %bb.0:
+; SPARC64-POPC-NEXT: add %o0, -1, %o1
+; SPARC64-POPC-NEXT: andn %o1, %o0, %o0
+; SPARC64-POPC-NEXT: retl
+; SPARC64-POPC-NEXT: popc %o0, %o0
+;
+; SPARC64-VIS3-LABEL: i64_nopoison:
+; SPARC64-VIS3: ! %bb.0:
+; SPARC64-VIS3-NEXT: add %o0, -1, %o1
+; SPARC64-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC64-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC64-VIS3-NEXT: mov 64, %o1
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: sub %o1, %o0, %o0
+ %ret = call i64 @llvm.cttz.i64(i64 %x, i1 false)
+ ret i64 %ret
+}
-attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
+define i64 @i64_poison(i64 %x) nounwind {
+; SPARC-LABEL: i64_poison:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: sethi 122669, %o2
+; SPARC-NEXT: or %o2, 305, %o2
+; SPARC-NEXT: sethi %hi(.LCPI3_0), %o3
+; SPARC-NEXT: cmp %o1, 0
+; SPARC-NEXT: bne .LBB3_2
+; SPARC-NEXT: add %o3, %lo(.LCPI3_0), %o3
+; SPARC-NEXT: ! %bb.1:
+; SPARC-NEXT: sub %g0, %o0, %o1
+; SPARC-NEXT: and %o0, %o1, %o0
+; SPARC-NEXT: smul %o0, %o2, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: ldub [%o3+%o0], %o0
+; SPARC-NEXT: add %o0, 32, %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov %g0, %o0
+; SPARC-NEXT: .LBB3_2:
+; SPARC-NEXT: sub %g0, %o1, %o0
+; SPARC-NEXT: and %o1, %o0, %o0
+; SPARC-NEXT: smul %o0, %o2, %o0
+; SPARC-NEXT: srl %o0, 27, %o0
+; SPARC-NEXT: ldub [%o3+%o0], %o1
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov %g0, %o0
+;
+; SPARC-POPC-LABEL: i64_poison:
+; SPARC-POPC: ! %bb.0:
+; SPARC-POPC-NEXT: sethi 122669, %o2
+; SPARC-POPC-NEXT: or %o2, 305, %o2
+; SPARC-POPC-NEXT: sethi %hi(.LCPI3_0), %o3
+; SPARC-POPC-NEXT: cmp %o1, 0
+; SPARC-POPC-NEXT: bne .LBB3_2
+; SPARC-POPC-NEXT: add %o3, %lo(.LCPI3_0), %o3
+; SPARC-POPC-NEXT: ! %bb.1:
+; SPARC-POPC-NEXT: sub %g0, %o0, %o1
+; SPARC-POPC-NEXT: and %o0, %o1, %o0
+; SPARC-POPC-NEXT: smul %o0, %o2, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: ldub [%o3+%o0], %o0
+; SPARC-POPC-NEXT: add %o0, 32, %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: mov %g0, %o0
+; SPARC-POPC-NEXT: .LBB3_2:
+; SPARC-POPC-NEXT: sub %g0, %o1, %o0
+; SPARC-POPC-NEXT: and %o1, %o0, %o0
+; SPARC-POPC-NEXT: smul %o0, %o2, %o0
+; SPARC-POPC-NEXT: srl %o0, 27, %o0
+; SPARC-POPC-NEXT: ldub [%o3+%o0], %o1
+; SPARC-POPC-NEXT: retl
+; SPARC-POPC-NEXT: mov %g0, %o0
+;
+; SPARC-VIS3-LABEL: i64_poison:
+; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: cmp %o1, 0
+; SPARC-VIS3-NEXT: bne .LBB3_2
+; SPARC-VIS3-NEXT: nop
+; SPARC-VIS3-NEXT: ! %bb.1:
+; SPARC-VIS3-NEXT: add %o0, -1, %o1
+; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: ba .LBB3_3
+; SPARC-VIS3-NEXT: mov 64, %o1
+; SPARC-VIS3-NEXT: .LBB3_2:
+; SPARC-VIS3-NEXT: add %o1, -1, %o0
+; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
+; SPARC-VIS3-NEXT: srl %o0, 0, %o0
+; SPARC-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -32, %o0
+; SPARC-VIS3-NEXT: mov 32, %o1
+; SPARC-VIS3-NEXT: .LBB3_3:
+; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov %g0, %o0
+;
+; SPARC64-LABEL: i64_poison:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: sub %g0, %o0, %o1
+; SPARC64-NEXT: and %o0, %o1, %o0
+; SPARC64-NEXT: sethi 3362647, %o1
+; SPARC64-NEXT: or %o1, 447, %o1
+; SPARC64-NEXT: sethi 34344, %o2
+; SPARC64-NEXT: or %o2, 914, %o2
+; SPARC64-NEXT: sllx %o2, 32, %o2
+; SPARC64-NEXT: or %o2, %o1, %o1
+; SPARC64-NEXT: mulx %o0, %o1, %o0
+; SPARC64-NEXT: srlx %o0, 58, %o0
+; SPARC64-NEXT: sethi %h44(.LCPI3_0), %o1
+; SPARC64-NEXT: add %o1, %m44(.LCPI3_0), %o1
+; SPARC64-NEXT: sllx %o1, 12, %o1
+; SPARC64-NEXT: add %o1, %l44(.LCPI3_0), %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: ldub [%o1+%o0], %o0
+;
+; SPARC64-POPC-LABEL: i64_poison:
+; SPARC64-POPC: ! %bb.0:
+; SPARC64-POPC-NEXT: add %o0, -1, %o1
+; SPARC64-POPC-NEXT: andn %o1, %o0, %o0
+; SPARC64-POPC-NEXT: retl
+; SPARC64-POPC-NEXT: popc %o0, %o0
+;
+; SPARC64-VIS3-LABEL: i64_poison:
+; SPARC64-VIS3: ! %bb.0:
+; SPARC64-VIS3-NEXT: add %o0, -1, %o1
+; SPARC64-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC64-VIS3-NEXT: lzcnt %o0, %o0
+; SPARC64-VIS3-NEXT: mov 64, %o1
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: sub %o1, %o0, %o0
+ %ret = call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ ret i64 %ret
+}
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