[llvm] [Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation (PR #135768)

[via llvm-commits]

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@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic | FileCheck %s
+
+define i32 @div_imm_non_zero(i32 signext %a) nounwind {
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yingopq wrote:

`-O3` would not generate `div+teq`.

https://github.com/llvm/llvm-project/pull/135768