[llvm] 72bc052 - [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)

[via llvm-commits]

Author: Brox Chen
Date: 2025-04-27T14:30:34-04:00
New Revision: 72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf

URL: https://github.com/llvm/llvm-project/commit/72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf
DIFF: https://github.com/llvm/llvm-project/commit/72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf.diff

LOG: [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)

We currently just need to shift down 32bit wwm registers. 

Previous check condition mistakenly select 16bit registers in true16
mode. Update check condition to skip the 16bit register in wmm reg
sorting

Added: 
    llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 0c1cd9ceddb02..e29aeb84f7669 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1650,7 +1650,7 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
     // are of 32-bit size. SIPreAllocateWWMRegs pass can add tuples into WWM
     // reserved registers.
     const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
-    if (TRI->getRegSizeInBits(*RC) > 32)
+    if (TRI->getRegSizeInBits(*RC) != 32)
       continue;
     SortedWWMVGPRs.push_back(Reg);
   }

diff  --git a/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
new file mode 100644
index 0000000000000..41d0029b7f1f1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            wwm_reg_skip_sort_16bit
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: wwm_reg_skip_sort_16bit
+    ; GCN: renamable $sgpr0 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+    ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; GCN-NEXT: renamable $sgpr1 = V_READLANE_B32 $vgpr0, 31
+    ; GCN-NEXT: renamable $sgpr2 = S_MOV_B32 0
+    ; GCN-NEXT: undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, 0, 0, killed $sgpr1, killed $sgpr2, 0, implicit $exec
+    ; GCN-NEXT: $exec_lo = EXIT_STRICT_WWM killed renamable $sgpr0
+    ; GCN-NEXT: early-clobber renamable $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
+    ; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $vgpr1
+    renamable $sgpr0 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+    $vgpr0 = IMPLICIT_DEF
+    renamable $sgpr1 = V_READLANE_B32 $vgpr0, 31
+    renamable $sgpr2 = S_MOV_B32 0
+    undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, 0, 0, killed $sgpr1, killed $sgpr2, 0, implicit $exec
+    $exec_lo = EXIT_STRICT_WWM killed renamable $sgpr0
+    early-clobber renamable $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
+    S_ENDPGM 0, implicit killed renamable $vgpr1
+...