[llvm] [Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation (PR #135768)

[via llvm-commits]

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@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic | FileCheck %s
+
+define i32 @div_imm_non_zero(i32 signext %a) nounwind {
+; CHECK-LABEL: div_imm_non_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -8
+; CHECK-NEXT:    sw $4, 4($sp)
+; CHECK-NEXT:    lw $1, 4($sp)
+; CHECK-NEXT:    addiu $2, $zero, 1234
+; CHECK-NEXT:    div $zero, $1, $2
+; CHECK-NEXT:    mflo $2
+; CHECK-NEXT:    addiu $sp, $sp, 8
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    nop
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4
+  %0 = load i32, ptr %a.addr, align 4
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yingopq wrote:

OK, applied.

https://github.com/llvm/llvm-project/pull/135768