[llvm] [AMDGPU] [PeepholeOpt] Eliminate unnecessary packing in wider f16 vectors for sdwa/opsel-able instruction (PR #137137)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 295726ddb..b8bb27430 100644
--- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -1456,54 +1456,66 @@ static bool checkForRightSrcRootAccess(MachineInstr *Def0MI,
                                        Register SrcRootReg,
                                        const SIInstrInfo *TII) {
   // As if could, the Def1MI would have been sdwa-ed
-  if(!TII->isSDWA(Def1MI->getOpcode()))
+  if (!TII->isSDWA(Def1MI->getOpcode()))
     return false;
 
-  MachineOperand *Def1Src0 = TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src0);
-  MachineOperand *Def1Src1 = TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src1);
-  MachineOperand *Def0Src0 = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0);
-  MachineOperand *Def0Src1 = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1);
-  
-  if(Def1Src0 && Def1Src0->isReg() && (Def1Src0->getReg() == SrcRootReg)) {
-    MachineOperand *Def1Src0Sel = TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src0_sel);
-    if(!Def1Src0Sel || (Def1Src0Sel->getImm() != AMDGPU::SDWA::SdwaSel::WORD_1))
+  MachineOperand *Def1Src0 =
+      TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src0);
+  MachineOperand *Def1Src1 =
+      TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src1);
+  MachineOperand *Def0Src0 =
+      TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0);
+  MachineOperand *Def0Src1 =
+      TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1);
+
+  if (Def1Src0 && Def1Src0->isReg() && (Def1Src0->getReg() == SrcRootReg)) {
+    MachineOperand *Def1Src0Sel =
+        TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src0_sel);
+    if (!Def1Src0Sel ||
+        (Def1Src0Sel->getImm() != AMDGPU::SDWA::SdwaSel::WORD_1))
       return false;
 
-    if(Def0Src0 && Def0Src0->isReg() && (Def0Src0->getReg() == SrcRootReg)) {
-      MachineOperand *Def0Src0Sel = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0_sel);
-      if(!Def0Src0Sel)
+    if (Def0Src0 && Def0Src0->isReg() && (Def0Src0->getReg() == SrcRootReg)) {
+      MachineOperand *Def0Src0Sel =
+          TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0_sel);
+      if (!Def0Src0Sel)
         return true;
-      if(Def0Src0Sel && Def0Src0Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
+      if (Def0Src0Sel && Def0Src0Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
         return true;
     }
 
-    if(Def0Src1 && Def0Src1->isReg() && (Def0Src1->getReg() == SrcRootReg)) {
-      MachineOperand *Def0Src1Sel = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1_sel);
-      if(!Def0Src1Sel)
+    if (Def0Src1 && Def0Src1->isReg() && (Def0Src1->getReg() == SrcRootReg)) {
+      MachineOperand *Def0Src1Sel =
+          TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1_sel);
+      if (!Def0Src1Sel)
         return true;
-      if(Def0Src1Sel && Def0Src1Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
+      if (Def0Src1Sel && Def0Src1Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
         return true;
     }
   }
 
-  if(Def1Src1 && Def1Src1->isReg() && (Def1Src1->getReg() == SrcRootReg)) {
-    MachineOperand *Def1Src1Sel = TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src1_sel);
-    if(!Def1Src1Sel || (Def1Src1Sel->getImm() != AMDGPU::SDWA::SdwaSel::WORD_1))
+  if (Def1Src1 && Def1Src1->isReg() && (Def1Src1->getReg() == SrcRootReg)) {
+    MachineOperand *Def1Src1Sel =
+        TII->getNamedOperand(*Def1MI, AMDGPU::OpName::src1_sel);
+    if (!Def1Src1Sel ||
+        (Def1Src1Sel->getImm() != AMDGPU::SDWA::SdwaSel::WORD_1))
       return false;
 
-    if(Def0Src0 && Def0Src0->isReg() && (Def0Src0->getReg() == SrcRootReg)) {
-      MachineOperand *Def0Src0Sel = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0_sel);
-      if(!Def0Src0Sel)
+    if (Def0Src0 && Def0Src0->isReg() && (Def0Src0->getReg() == SrcRootReg)) {
+      MachineOperand *Def0Src0Sel =
+          TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src0_sel);
+      if (!Def0Src0Sel)
         return true;
-      if(Def0Src0Sel && Def0Src0Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
+      if (Def0Src0Sel && Def0Src0Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
         return true;
     }
 
-    if(Def0Src1 && Def0Src1->isReg() && (Def0Src1->getReg() == SrcRootReg)) {
-      MachineOperand *Def0Src1Sel = TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1_sel);
-      if(!Def0Src1Sel)
+    if (Def0Src1 && Def0Src1->isReg() && (Def0Src1->getReg() == SrcRootReg)) {
+      MachineOperand *Def0Src1Sel =
+          TII->getNamedOperand(*Def0MI, AMDGPU::OpName::src1_sel);
+      if (!Def0Src1Sel)
         return true;
-      if(Def0Src1Sel && Def0Src1Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
+      if (Def0Src1Sel && Def0Src1Sel->getImm() == AMDGPU::SDWA::SdwaSel::WORD_0)
         return true;
     }
   }
@@ -1712,7 +1724,7 @@ void SIPeepholeSDWA::eliminateFP16Packing(MachineBasicBlock &MBB,
       if (SrcRootMOReg == AMDGPU::NoRegister)
         continue;
 
-      // Also we need to ensure that each of the DefXRootMI should access the 
+      // Also we need to ensure that each of the DefXRootMI should access the
       // lower and upper half word of SrcRootMOReg respectively.
       if (!checkForRightSrcRootAccess(Def0RootMI, Def1RootMI, SrcRootMOReg,
                                       TII))

``````````

</details>


https://github.com/llvm/llvm-project/pull/137137