[llvm] [AMDGPU] Fix undefined scc register in successor block of SI_KILL terminators (PR #134718)

[via llvm-commits]

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@@ -47,6 +47,8 @@ static std::pair<bool, bool> runImpl(MachineFunction &MF) {
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
 
+  TLI->finalizeLowering(MF);
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mssefat wrote:

I think we need this reordering. Without this reordering, llvm::addLiveIns() invoked from MachineBasicBlock::splitAt() triggers an assertion failure due to the check for reservedRegsFrozen() when reserved registers are not yet finalized. 

https://github.com/llvm/llvm-project/pull/134718