[lldb] [llvm] Add RISC-V CPU type and CPU subtype to llvm & lldb (PR #136785)

[Jonas Devlieghere via llvm-commits]

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@@ -113,6 +113,14 @@ TEST(ArchSpecTest, TestSetTriple) {
                   .consume_front("powerpc-apple-darwin"));
   EXPECT_EQ(ArchSpec::eCore_ppc_ppc970, AS.GetCore());
 
+  AS = ArchSpec();
+  EXPECT_TRUE(AS.SetTriple("24-0-apple-unknown"));
+  EXPECT_EQ(uint32_t(llvm::MachO::CPU_TYPE_RISCV), AS.GetMachOCPUType());
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JDevlieghere wrote:

It's the "24-0" which represent the CPU type (24) and the subtype (0).

https://github.com/llvm/llvm-project/pull/136785