[llvm] [Xtensa] Implement Xtensa S32C1I Option and atomics lowering. (PR #137134)

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git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp llvm/lib/Target/Xtensa/XtensaISelLowering.cpp llvm/lib/Target/Xtensa/XtensaISelLowering.h llvm/lib/Target/Xtensa/XtensaSubtarget.h llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
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diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index f3873ca4d..928a0c623 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -114,9 +114,9 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
 }
 
 const MCPhysReg SRDecoderTable[] = {
-    Xtensa::SAR, 3, Xtensa::ACCLO,      16, Xtensa::ACCHI,       17,
-    Xtensa::SCOMPARE1, 12, Xtensa::M0,  32, Xtensa::M1,          33,
-    Xtensa::M2,        34, Xtensa::M3,  35, Xtensa::WINDOWBASE,  72,
+    Xtensa::SAR,         3,  Xtensa::ACCLO,   16, Xtensa::ACCHI,      17,
+    Xtensa::SCOMPARE1,   12, Xtensa::M0,      32, Xtensa::M1,         33,
+    Xtensa::M2,          34, Xtensa::M3,      35, Xtensa::WINDOWBASE, 72,
     Xtensa::WINDOWSTART, 73, Xtensa::ATOMCTL, 99};
 
 static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index e74c5c1e6..1dc8a2369 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -175,7 +175,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::VACOPY, MVT::Other, Custom);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
-    // to have the best chance and doing something good with fences custom lower
+  // to have the best chance and doing something good with fences custom lower
   // them
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
 
@@ -1276,10 +1276,10 @@ bool XtensaTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
 }
 
 SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op,
-  SelectionDAG &DAG) const {
-SDLoc DL(Op);
-SDValue Chain = Op.getOperand(0);
-return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain);
+                                                SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Chain = Op.getOperand(0);
+  return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain);
 }
 
 SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index 0e5582526..6d610c99f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -178,7 +178,7 @@ private:
 
   MachineBasicBlock *emitSelectCC(MachineInstr &MI,
                                   MachineBasicBlock *BB) const;
-                                  MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB,
+  MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB,
                                     int isByteOperand) const;
   MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB,
                                        int isByteOperand) const;

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https://github.com/llvm/llvm-project/pull/137134