[llvm] ee2aba7 - AMDGPU: Use poison in some lowering contexts (#137325)
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Fri Apr 25 07:04:39 PDT 2025
Author: Matt Arsenault
Date: 2025-04-25T16:04:34+02:00
New Revision: ee2aba7cc6359f7657db2ab6723e834b94ac9306
URL: https://github.com/llvm/llvm-project/commit/ee2aba7cc6359f7657db2ab6723e834b94ac9306
DIFF: https://github.com/llvm/llvm-project/commit/ee2aba7cc6359f7657db2ab6723e834b94ac9306.diff
LOG: AMDGPU: Use poison in some lowering contexts (#137325)
This replaces most of the places that use undef. I left alone
the cases that require additional thought.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index aed5571dfb27c..c05ba42d999e9 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2226,7 +2226,7 @@ SDValue SITargetLowering::getPreloadedValue(
// It's undefined behavior if a function marked with the amdgpu-no-*
// attributes uses the corresponding intrinsic.
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
}
return loadInputValue(DAG, RC, VT, SDLoc(DAG.getEntryNode()), *Reg);
@@ -2962,7 +2962,7 @@ SDValue SITargetLowering::LowerFormalArguments(
for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
const ISD::InputArg &Arg = Ins[i];
if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) || IsError) {
- InVals.push_back(DAG.getUNDEF(Arg.VT));
+ InVals.push_back(DAG.getPOISON(Arg.VT));
continue;
}
@@ -3446,12 +3446,12 @@ void SITargetLowering::passSpecialInputs(
if (Id.has_value()) {
InputReg = DAG.getConstant(*Id, DL, ArgVT);
} else {
- InputReg = DAG.getUNDEF(ArgVT);
+ InputReg = DAG.getPOISON(ArgVT);
}
} else {
// We may have proven the input wasn't needed, although the ABI is
// requiring it. We just need to allocate the register appropriately.
- InputReg = DAG.getUNDEF(ArgVT);
+ InputReg = DAG.getPOISON(ArgVT);
}
if (OutgoingArg->isRegister()) {
@@ -3531,7 +3531,7 @@ void SITargetLowering::passSpecialInputs(
// ID, but the calling function does not have it (e.g a graphics function
// calling a C calling convention function). This is illegal, but we need
// to produce something.
- InputReg = DAG.getUNDEF(MVT::i32);
+ InputReg = DAG.getPOISON(MVT::i32);
} else {
// Workitem ids are already packed, any of present incoming arguments
// will carry all required fields.
@@ -3777,7 +3777,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
if (Callee.isUndef() || isNullConstant(Callee)) {
if (!CLI.IsTailCall) {
for (ISD::InputArg &Arg : CLI.Ins)
- InVals.push_back(DAG.getUNDEF(Arg.VT));
+ InVals.push_back(DAG.getPOISON(Arg.VT));
}
return Chain;
@@ -6139,7 +6139,7 @@ static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
// Pad illegal v1i16/v3fi6 to v4i16
if ((LoadVT.getVectorNumElements() % 2) == 1)
- Elts.push_back(DAG.getUNDEF(MVT::i16));
+ Elts.push_back(DAG.getPOISON(MVT::i16));
Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
@@ -6231,7 +6231,7 @@ static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N,
EVT VT = N->getValueType(0);
unsigned CondCode = N->getConstantOperandVal(3);
if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
@@ -6266,7 +6266,7 @@ static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N,
unsigned CondCode = N->getConstantOperandVal(3);
if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
SDValue Src0 = N->getOperand(1);
SDValue Src1 = N->getOperand(2);
@@ -7343,7 +7343,7 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
if (UserSGPR == AMDGPU::NoRegister) {
// We probably are in a function incorrectly marked with
// amdgpu-no-queue-ptr. This is undefined.
- return DAG.getUNDEF(MVT::i32);
+ return DAG.getPOISON(MVT::i32);
}
SDValue QueuePtr =
@@ -7465,8 +7465,7 @@ SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
// global <-> flat are no-ops and never emitted.
// Invalid casts are poison.
- // TODO: Should return poison
- return DAG.getUNDEF(Op->getValueType(0));
+ return DAG.getPOISON(Op->getValueType(0));
}
// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
@@ -7808,7 +7807,7 @@ SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
NewMaskIdx1 += NewSrcNumElts;
Result1 = SubVec1;
} else {
- Result1 = DAG.getUNDEF(PackVT);
+ Result1 = DAG.getPOISON(PackVT);
}
SDValue Shuf = DAG.getVectorShuffle(PackVT, SL, Result0, Result1,
@@ -7841,7 +7840,7 @@ SDValue SITargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
SDValue SVal = Op.getOperand(0);
EVT ResultVT = Op.getValueType();
EVT SValVT = SVal.getValueType();
- SDValue UndefVal = DAG.getUNDEF(SValVT);
+ SDValue UndefVal = DAG.getPOISON(SValVT);
SDLoc SL(Op);
SmallVector<SDValue, 8> VElts;
@@ -8065,7 +8064,7 @@ static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
"non-hsa intrinsic with hsa target",
DL.getDebugLoc());
DAG.getContext()->diagnose(BadIntrin);
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
}
static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
@@ -8074,7 +8073,7 @@ static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
"intrinsic not supported on subtarget",
DL.getDebugLoc());
DAG.getContext()->diagnose(BadIntrin);
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
}
static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
@@ -8099,7 +8098,7 @@ static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
VecElts[i] = Elt;
}
for (unsigned i = Elts.size(); i < NumElts; ++i)
- VecElts[i] = DAG.getUNDEF(MVT::f32);
+ VecElts[i] = DAG.getPOISON(MVT::f32);
if (NumElts == 1)
return VecElts[0];
@@ -8117,7 +8116,7 @@ static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
else
Elts.push_back(Src);
- SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
+ SDValue Undef = DAG.getPOISON(SrcVT.getScalarType());
while (ExtraElts--)
Elts.push_back(Undef);
@@ -8368,7 +8367,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
// occupies full 32-bit.
SDValue Bias = DAG.getBuildVector(
MVT::v2f16, DL,
- {Op.getOperand(ArgOffset + I), DAG.getUNDEF(MVT::f16)});
+ {Op.getOperand(ArgOffset + I), DAG.getPOISON(MVT::f16)});
VAddrs.push_back(Bias);
} else {
assert((!IsA16 || Intr->NumBiasArgs == 0 || I != Intr->BiasIndex) &&
@@ -8498,7 +8497,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
// type
if (DMaskLanes == 0 && !BaseOpcode->Store) {
// This is a no-op load. This can be eliminated
- SDValue Undef = DAG.getUNDEF(Op.getValueType());
+ SDValue Undef = DAG.getPOISON(Op.getValueType());
if (isa<MemSDNode>(Op))
return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
return Undef;
@@ -8743,7 +8742,7 @@ SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
// It's undefined behavior if a function marked with the amdgpu-no-*
// attributes uses the corresponding intrinsic.
if (!Arg)
- return DAG.getUNDEF(Op->getValueType(0));
+ return DAG.getPOISON(Op->getValueType(0));
SDValue Val = loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
SDLoc(DAG.getEntryNode()), Arg);
@@ -8786,7 +8785,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
MF.getFunction(), "unsupported hsa intrinsic without hsa target",
DL.getDebugLoc());
DAG.getContext()->diagnose(BadIntrin);
- return DAG.getUNDEF(VT);
+ return DAG.getPOISON(VT);
}
auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr
@@ -9661,7 +9660,7 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
if (!UseNSA) {
// Build a single vector containing all the operands so far prepared.
if (NumVAddrDwords > 12) {
- SDValue Undef = DAG.getUNDEF(MVT::i32);
+ SDValue Undef = DAG.getPOISON(MVT::i32);
Ops.append(16 - Ops.size(), Undef);
}
assert(Ops.size() >= 8 && Ops.size() <= 12);
@@ -9847,13 +9846,13 @@ SDValue SITargetLowering::handleD16VData(SDValue VData, SelectionDAG &DAG,
// Handle v3i16
unsigned I = Elts.size() / 2;
SDValue Pair = DAG.getBuildVector(MVT::v2i16, DL,
- {Elts[I * 2], DAG.getUNDEF(MVT::i16)});
+ {Elts[I * 2], DAG.getPOISON(MVT::i16)});
SDValue IntPair = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Pair);
PackedElts.push_back(IntPair);
}
// Pad using UNDEF
- PackedElts.resize(Elts.size(), DAG.getUNDEF(MVT::i32));
+ PackedElts.resize(Elts.size(), DAG.getPOISON(MVT::i32));
// Build final vector
EVT VecVT =
@@ -9900,7 +9899,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
return SDValue();
const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(6));
- SDValue Undef = DAG.getUNDEF(MVT::f32);
+ SDValue Undef = DAG.getPOISON(MVT::f32);
const SDValue Ops[] = {
Op.getOperand(2), // tgt
DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0), // src0
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