The Week Of Monday 21 April 2025 Archives by date

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Starting: Mon Apr 21 00:01:49 PDT 2025
Ending: Tue Apr 22 02:54:47 PDT 2025
Messages: 1242

• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [llvm] b6820c3 - [MachinePipeliner] Remove UB from tests (NFC) (#123169)   via llvm-commits
• [llvm] [MachinePipeliner] Remove UB from tests (NFC) (PR #123169)   Ryotaro Kasuga via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   A. Jiang via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   A. Jiang via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   A. Jiang via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   A. Jiang via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] [COFF] Preserve UniqueID used to create MCSectionCOFF (PR #123869)   Haohai Wen via llvm-commits
• [llvm] [PseudoProbe] Add PseudoProbeDescUpdatePass (PR #99839)   Haohai Wen via llvm-commits
• [clang] [llvm] [clang][AVR] Improve compatibility of inline assembly with avr-gcc (PR #136534)   Ben Shi via llvm-commits
• [llvm] [COFF] Preserve UniqueID used to create MCSectionCOFF (PR #123869)   Haohai Wen via llvm-commits
• [clang] [llvm] [clang][AVR] Improve compatibility of inline assembly with avr-gcc (PR #136534)   Ben Shi via llvm-commits
• [clang] [llvm] [clang][AVR] Improve compatibility of inline assembly with avr-gcc (PR #136534)   Ben Shi via llvm-commits
• [clang] [llvm] DO NOT MERGE: Identify places that need reserve. (PR #136543)   Kazu Hirata via llvm-commits
• [clang] [llvm] [clang][AVR] Improve compatibility of inline assembly with avr-gcc (PR #136534)   Sergei Barannikov via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] [LoongArch] Pre-commit for widen shuffle mask (PR #136544)   via llvm-commits
• [llvm] [LoongArch] Pre-commit for widen shuffle mask (PR #136544)   via llvm-commits
• [llvm] [MIPS]Remove unnecessary SLL instructions on MIPS64el (PR #109386)   via llvm-commits
• [clang] [llvm] DO NOT MERGE: Identify places that need reserve. (PR #136543)   Kazu Hirata via llvm-commits
• [llvm] [LoongArch] Pre-commit for widen shuffle mask (PR #136544)   via llvm-commits
• [llvm] [MIPS]Remove unnecessary SLL instructions on MIPS64el (PR #109386)   via llvm-commits
• [llvm] 4853bf0 - [LoongArch] Lower build_vector to broadcast load if possible (#135896)   via llvm-commits
• [llvm] [LoongArch] Lower build_vector to broadcast load if possible (PR #135896)   via llvm-commits
• [llvm] 053451c - [RISCV] Handle scalarized reductions in getArithmeticReductionCost   Luke Lau via llvm-commits
• [llvm] [RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (PR #114250)   Luke Lau via llvm-commits
• [llvm] [HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (PR #135925)   Abinaya Saravanan via llvm-commits
• [llvm] [LoongArch] Lower build_vector to broadcast load if possible (PR #135896)   LLVM Continuous Integration via llvm-commits
• [llvm] [IRCE] Fix '"Instruction does not dominate all uses!" after IRCE pass #63984' (PR #136505)   Nikita Popov via llvm-commits
• [llvm] [MIPS]Remove unnecessary SLL instructions on MIPS64el (PR #109386)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Check for AMXTile (PR #136507)   Simon Pilgrim via llvm-commits
• [llvm] 47ca7f1 - [X86] Remove unused BitVector TILERegs (NFC) (#136508)   via llvm-commits
• [llvm] [X86] Remove unused BitVector TILERegs (NFC) (PR #136508)   Simon Pilgrim via llvm-commits
• [llvm] [IRCE] Fix '"Instruction does not dominate all uses!" after IRCE pass #63984' (PR #136505)   via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Matt Arsenault via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Matt Arsenault via llvm-commits
• [llvm] [CostModel] Remove optional from InstructionCost::getValue() (PR #135596)   Simon Pilgrim via llvm-commits
• [llvm] [LoopVectorizer] Prune VFs based on plan register pressure (PR #132190)   Luke Lau via llvm-commits
• [llvm] [CostModel] Remove optional from InstructionCost::getValue() (PR #135596)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Use llvm::SmallVector::pop_back_val (NFC) (PR #136533)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [X86] Remove unused BitVector TILERegs (NFC) (PR #136508)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [IRCE] Fix '"Instruction does not dominate all uses!" after IRCE pass #63984' (PR #136505)   via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   Matt Arsenault via llvm-commits
• [llvm] [IRCE] Fix '"Instruction does not dominate all uses!" after IRCE pass #63984' (PR #136505)   via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Sam Elliott via llvm-commits
• [llvm] [X86][Combine] Ensure single use chain in extract-load combine (PR #136520)   Simon Pilgrim via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   Luke Lau via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   Luke Lau via llvm-commits
• [llvm] [X86][SelectionDAG] Fix the Gather's base and index by modifying the Scale value (PR #134979)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Christudasan Devadasan via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Christudasan Devadasan via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Christudasan Devadasan via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   Liao Chunyu via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Matt Arsenault via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   Sudharsan Veeravalli via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Luke Lau via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Luke Lau via llvm-commits
• [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)   Matt Arsenault via llvm-commits
• [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)   Matt Arsenault via llvm-commits
• [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)   Matt Arsenault via llvm-commits
• [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Jim Lin via llvm-commits
• [llvm] [AMDGPU] add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [AMDGPU] add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] insert readfirstlane in the function returns in sgpr (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] insert readfirstlane in the function returns in sgpr (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Marius Kamp via llvm-commits
• [llvm] [X86] Distribute Certain Bitwise Operations over SELECT (PR #136555)   Marius Kamp via llvm-commits
• [llvm] [X86] Distribute Certain Bitwise Operations over SELECT (PR #136555)   Marius Kamp via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   via llvm-commits
• [llvm] InstCombine: Fold samesign ult to slt with added constant when the range is known (PR #134556)   Rajagopalan Gangadharan via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   Sam Elliott via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Matt Arsenault via llvm-commits
• [llvm] c347ad2 - [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (#136552)   via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   Liao Chunyu via llvm-commits
• [clang] [llvm] Add smcntrpmf extension (PR #136556)   Liao Chunyu via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [clang] [llvm] Add smcntrpmf extension (PR #136556)   via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Liao Chunyu via llvm-commits
• [llvm] [RISCV] Add range metadata for atomic load of boolean type. (PR #136502)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Marius Kamp via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Christudasan Devadasan via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Christudasan Devadasan via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Sam Elliott via llvm-commits
• [llvm] 940108b - [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (#136551)   via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   Christudasan Devadasan via llvm-commits
• [llvm] [llvm-extract] support unnamed bbs. (PR #135140)   Benjamin Maxwell via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Pengcheng Wang via llvm-commits
• [llvm] Added APInt::clearBits() method #136550 (PR #136557)   via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] Added APInt::clearBits() method #136550 (PR #136557)   via llvm-commits
• [llvm] Added APInt::clearBits() method #136550 (PR #136557)   via llvm-commits
• [llvm] Added APInt::clearBits() method #136550 (PR #136557)   via llvm-commits
• [llvm] [ConstraintElim] Add facts about non-poison intrinsics on demand (PR #136558)   Yingwei Zheng via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Remove `AND` mask generated by `( zext ( atomic_load ) )` by replacing the load with `zextload` for orderings not stronger then monotonic. (PR #136502)   Jan Górski via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Jim Lin via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Matt Arsenault via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   YunQiang Su via llvm-commits
• [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)   LLVM Continuous Integration via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Jim Lin via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Jim Lin via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Implement vop3p complex pattern optmization for gisel (PR #130234)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Implement vop3p complex pattern optmization for gisel (PR #130234)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Implement vop3p complex pattern optmization for gisel (PR #130234)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)   Matt Arsenault via llvm-commits
• [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)   Matt Arsenault via llvm-commits
• [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)   Matt Arsenault via llvm-commits
• [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)   Matt Arsenault via llvm-commits
• [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)   Matt Arsenault via llvm-commits
• [llvm] [InstSimplify] Fold `getelementptr inbounds null, idx -> null` (PR #130742)   Madhur Amilkanthwar via llvm-commits
• [llvm] [ConstraintElim] Add facts about non-poison intrinsics on demand (PR #136558)   Yingwei Zheng via llvm-commits
• [llvm] [GlobalISel] Add `combine` action for C++ combine rules (PR #135941)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [LangRef][IR] Fix default AS documentation for allocas without explicit AS (PR #135942)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   Simon Pilgrim via llvm-commits
• [llvm] [CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (PR #102731)   Matt Arsenault via llvm-commits
• [llvm] [CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (PR #102731)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Matt Arsenault via llvm-commits
• [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Matt Arsenault via llvm-commits
• [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)   LLVM Continuous Integration via llvm-commits
• [llvm] [CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (PR #102731)   Sergei Barannikov via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (PR #135817)   Paul Walker via llvm-commits
• [llvm] [InstSimplify] Fold `getelementptr inbounds null, idx -> null` (PR #130742)   Luke Lau via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Matt Arsenault via llvm-commits
• [llvm] [CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (PR #102731)   Matt Arsenault via llvm-commits
• [llvm] [AArch64][GlobalISel] Adopt some Ld* patterns to reduce codegen regressions (PR #135492)   Matt Arsenault via llvm-commits
• [libcxxabi] [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)   Luke Lau via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   via llvm-commits
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• [llvm] [RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (PR #114250)   Harald van Dijk via llvm-commits
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• [flang] [llvm] [mlir] [MLIR][OpenMP] Lowering nontemporal clause to LLVM IR for SIMD directive (PR #118751)   Kaviya Rajendiran via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Matt Arsenault via llvm-commits
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• [llvm] [AMDGPU] Implement IR expansion for frem instruction (PR #130988)   Matt Arsenault via llvm-commits
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• [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)   Matt Arsenault via llvm-commits
• [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)   Matt Arsenault via llvm-commits
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• [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)   Matt Arsenault via llvm-commits
• [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)   Matt Arsenault via llvm-commits
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• [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)   Matt Arsenault via llvm-commits
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• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
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• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   via llvm-commits
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• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   Matt Arsenault via llvm-commits
• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   Matt Arsenault via llvm-commits
• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   Matt Arsenault via llvm-commits
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• [llvm] InstCombine: Avoid counting uses of constants (PR #136566)   Yingwei Zheng via llvm-commits
• [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)   Jim Lin via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
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• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
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• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
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• [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)   Jim Lin via llvm-commits
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• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
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• [llvm] [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (PR #136015)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (PR #136015)   Mircea Trofin via llvm-commits
• [llvm] cfc2b0d - [llvm] Use llvm::SmallVector::pop_back_val (NFC) (#136533)   via llvm-commits
• [llvm] [llvm] Use llvm::SmallVector::pop_back_val (NFC) (PR #136533)   Kazu Hirata via llvm-commits
• [llvm] e1bb7f6 - [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (#136456)   via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   Rahul Joshi via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   Matt Arsenault via llvm-commits
• [llvm] [InstrRef] Preserve debug instr num in aarch64-ldst-opt. (PR #136009)   Jeremy Morse via llvm-commits
• [llvm] [InstrRef] Preserve debug instr num in aarch64-ldst-opt. (PR #136009)   Jeremy Morse via llvm-commits
• [llvm] [InstrRef] Preserve debug instr num in aarch64-ldst-opt. (PR #136009)   Jeremy Morse via llvm-commits
• [llvm] [InstrRef] Preserve debug instr num in aarch64-ldst-opt. (PR #136009)   Jeremy Morse via llvm-commits
• [llvm] [JITLink][AArch32] Add explicit visibility macros to functions needed by unittests (PR #116557)   Andrew Rogers via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (PR #136015)   Mircea Trofin via llvm-commits
• [llvm] [LLVM] Pass correct target to LLVM_RUNTIMES_TARGET for runtimes (PR #136572)   Joseph Huber via llvm-commits
• [llvm] [AArch64] Replace 64-bit MADD with [SU]MADDL when possible (PR #135926)   Yuri Gribov via llvm-commits
• [llvm] 93b74f7 - [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (#136015)   via llvm-commits
• [llvm] [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (PR #136015)   Mircea Trofin via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [NFC][LLVM][TableGen] Eliminate inheritance from std::vector (PR #136573)   Rahul Joshi via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Shilei Tian via llvm-commits
• [llvm] [LLVM] Cleanup pass initialization for Analysis passes (PR #135858)   Rahul Joshi via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   LLVM Continuous Integration via llvm-commits
• [llvm] [PowerPC] Intrinsics and tests for dmr insert/extract (PR #135653)   Maryam Moghadas via llvm-commits
• [llvm] [PowerPC] Intrinsics and tests for dmr insert/extract (PR #135653)   Maryam Moghadas via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)   Craig Topper via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Shilei Tian via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (PR #129890)   Anatoly Trosinenko via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Min-Yih Hsu via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Min-Yih Hsu via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Min-Yih Hsu via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Min-Yih Hsu via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Min-Yih Hsu via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Shilei Tian via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   LLVM Continuous Integration via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   Qinkun Bao via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Simon Pilgrim via llvm-commits
• [llvm] [BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (PR #129890)   Anatoly Trosinenko via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Shilei Tian via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)   Elizaveta Noskova via llvm-commits
• [llvm] 76ced7f - [AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)   via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV32. (PR #136577)   Craig Topper via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV32. (PR #136577)   via llvm-commits
• [llvm] [AMDGPU] Add SchedGroupBarrier::PACK for packed math (PR #132432)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Add SchedGroupBarrier::PACK for packed math (PR #132432)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [NFC][LLVM][TableGen] Eliminate inheritance from std::vector (PR #136573)   Rahul Joshi via llvm-commits
• [llvm] [NFC][LLVM][TableGen] Eliminate inheritance from std::vector (PR #136573)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Matt Arsenault via llvm-commits
• [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV32. (PR #136577)   Alexander Richardson via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   LLVM Continuous Integration via llvm-commits
• [llvm] [PAC][InstCombine] Replace auth+sign with resign (PR #130807)   Anatoly Trosinenko via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   LLVM Continuous Integration via llvm-commits
• [llvm] [PAC][InstCombine] Replace auth+sign with resign (PR #130807)   Anatoly Trosinenko via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)   via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Craig Topper via llvm-commits
• [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)   Justin Bogner via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Min-Yih Hsu via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Craig Topper via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (PR #136575)   via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Jan Patrick Lehr via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Min-Yih Hsu via llvm-commits
• [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)   Rainer Orth via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV32. (PR #136577)   Sam Elliott via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [clang] [llvm] [HLSL] Implement the `faceforward` intrinsic (PR #135878)   Farzon Lotfi via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV64. (PR #136577)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)   Jim Lin via llvm-commits
• [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)   Jim Lin via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Krzysztof Parzyszek via llvm-commits
• [llvm] b95ec24 - [SDAG] Handle insert_subvector in isKnownNeverNaN (#131989)   via llvm-commits
• [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)   Jim Lin via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   Alexey Samsonov via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   via llvm-commits
• [llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)   Changpeng Fang via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)   Changpeng Fang via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   via llvm-commits
• [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Min-Yih Hsu via llvm-commits
• [llvm] 5739a22 - [VPlan] Also duplicated scalar-steps when it enables sinking scalars. (#136021)   via llvm-commits
• [llvm] [VPlan] Also duplicated scalar-steps when it enables sinking scalars. (PR #136021)   Florian Hahn via llvm-commits
• [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)   Min-Yih Hsu via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (PR #135078)   Brox Chen via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   Ikhlas Ajbar via llvm-commits
• [llvm] [RISCV] Use ri.vzip2{a, b} for interleave2 if available (PR #136364)   Philip Reames via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Craig Topper via llvm-commits
• [llvm] [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a, b} (PR #136463)   Philip Reames via llvm-commits
• [llvm] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Shilei Tian via llvm-commits
• [llvm] [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a, b} (PR #136463)   Philip Reames via llvm-commits
• [llvm] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Shilei Tian via llvm-commits
• [llvm] [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a, b} (PR #136463)   Philip Reames via llvm-commits
• [llvm] [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a, b} (PR #136463)   Philip Reames via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Florian Hahn via llvm-commits
• [llvm] [DebugInfo][DWARF] Emit DW_AT_abstract_origin for concrete/inlined DW_TAG_lexical_blocks (PR #136205)   David Blaikie via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Sam Elliott via llvm-commits
• [llvm] 3e5a9d9 - [VPlan] Rename setFlags -> applyFlags (NFC).   Florian Hahn via llvm-commits
• [clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of global constants (PR #134399)   Nick Sarnie via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (PR #136575)   Matt Arsenault via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Craig Topper via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   Florian Hahn via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [llvm] [LLVM] Update handling of default runtime targets (PR #136591)   Joseph Huber via llvm-commits
• [llvm] [VPlan] Remove ILV::sinkScalarOperands. (PR #136023)   Florian Hahn via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   via llvm-commits
• [llvm] [llvm] Construct SmallVector with iterator ranges (NFC) (PR #136460)   David Blaikie via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Remove ILV::sinkScalarOperands. (PR #136023)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Remove ILV::sinkScalarOperands. (PR #136024)   Florian Hahn via llvm-commits
• [llvm] [msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (PR #136260)   Florian Mayer via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)   Nick Sarnie via llvm-commits
• [clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)   Nick Sarnie via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Sam Elliott via llvm-commits
• [llvm] msm2 (PR #136593)   Prabhu Rajasekaran via llvm-commits
• [llvm] msm2 (PR #136593)   via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Philip Reames via llvm-commits
• [llvm] msm2 (PR #136593)   Prabhu Rajasekaran via llvm-commits
• [llvm] [NFC][llvm] Remove duplicate isUEFI check (PR #136593)   Prabhu Rajasekaran via llvm-commits
• [llvm] [NFC][llvm] Remove duplicate isUEFI check (PR #136593)   Prabhu Rajasekaran via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [llvm] 4c0ea47 - [RISCV] Report error if Zilsd is used on RV64. (#136577)   via llvm-commits
• [llvm] [RISCV] Report error if Zilsd is used on RV64. (PR #136577)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Philip Reames via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Philip Reames via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Philip Reames via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] 9968ba8 - Revert "[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)"   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Shilei Tian via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   LLVM Continuous Integration via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] e0c1e23 - [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (#136575)   via llvm-commits
• [llvm] [TTI] Constify BasicTTIImplBase::thisT() (NFCI) (PR #136575)   Sergei Barannikov via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro to annotate friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Alexey Bataev via llvm-commits
• [llvm] [LLVM] Update handling of default runtime targets (PR #136591)   Joseph Huber via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [AArch64][GlobalISel] Perfect Shuffles (PR #106446)   Matt Arsenault via llvm-commits
• [llvm] [AArch64][GlobalISel] Perfect Shuffles (PR #106446)   Matt Arsenault via llvm-commits
• [llvm] [InstSimplify] Fold `getelementptr inbounds null, idx -> null` (PR #130742)   Eli Friedman via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Shilei Tian via llvm-commits
• [libc] [llvm] [libc] Fix passing the full runtime target for multilibs (PR #136208)   Joseph Huber via llvm-commits
• [libcxxabi] [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)   Philip Reames via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   Sergei Barannikov via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Krzysztof Parzyszek via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   Sergei Barannikov via llvm-commits
• [llvm] [RISCV] Simplify fixup kinds that force relocations (PR #136088)   Mariusz Borsa via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Gheorghe-Teodor Bercea via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] [SLP]Prefer segmented/deinterleaved loads to strided and fix codegen (PR #135058)   Alexey Bataev via llvm-commits
• [libcxxabi] [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (PR #136600)   Craig Topper via llvm-commits
• [llvm] [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (PR #136600)   via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   Matt Arsenault via llvm-commits
• [llvm] 99e4b39 - [LLVM] Cleanup pass initialization for Analysis passes (#135858)   via llvm-commits
• [llvm] [LLVM] Cleanup pass initialization for Analysis passes (PR #135858)   Rahul Joshi via llvm-commits
• [llvm] [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (PR #136600)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][MC] add fake16 error and promote test (PR #135984)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] add fake16 error and promote test (PR #135984)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] add fake16 error and promote test (PR #135984)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] add fake16 error and promote test (PR #135984)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] update mc test of a few vop1 t16 inst (PR #135588)   Brox Chen via llvm-commits
• [llvm] 1b4919d - [gn] port e1bb7f6ddec375   Nico Weber via llvm-commits
• [llvm] [WebAssembly] Enable a limited amount of stackification for debug code (PR #136510)   via llvm-commits
• [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Craig Topper via llvm-commits
• [llvm] 8c83355 - [VPlan] Handle VPIRPhi in VPRecipeBase::isPhi (NFC).   Florian Hahn via llvm-commits
• [llvm] [LLVM] Cleanup pass initialization for Analysis passes (PR #135858)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Craig Topper via llvm-commits
• [llvm] [WebAssembly] Enable a limited amount of stackification for debug code (PR #136510)   via llvm-commits
• [llvm] [llvm] Use llvm::less_first and llvm::less_second (NFC) (PR #136272)   Vladimir Vereschaka via llvm-commits
• [llvm] [WebAssembly] Enable a limited amount of stackification for debug code (PR #136510)   via llvm-commits
• [llvm] [WebAssembly] Enable a limited amount of stackification for debug code (PR #136510)   via llvm-commits
• [llvm] c1049e4 - [AMDGPU] Correct VOP3P encoding. NFC. (#136005)   via llvm-commits
• [llvm] [AMDGPU] Correct VOP3P encoding. NFC. (PR #136005)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)   via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   Michael Jones via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)   Joseph Huber via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro to annotate friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [clang] [llvm] [SROA] Vector promote some memsets (PR #133301)   via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Support for DLL export (PR #136014)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Support for DLL export (PR #136014)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Support for DLL export (PR #136014)   Andrew Rogers via llvm-commits
• [llvm] [RISCV] Simplify fixup kinds that force relocations (PR #136088)   Mariusz Borsa via llvm-commits
• [llvm] [AMDGPU] Correct VOP3P encoding. NFC. (PR #136005)   LLVM Continuous Integration via llvm-commits
• [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   Alexey Samsonov via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   Michael Jones via llvm-commits
• [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)   Alexey Samsonov via llvm-commits
• [llvm] AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (PR #136609)   Changpeng Fang via llvm-commits
• [flang] [llvm] [flang][openacc] Make async clause behavior homogenous (PR #136610)   Valentin Clement バレンタイン クレメン via llvm-commits
• [llvm] AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (PR #136609)   via llvm-commits
• [llvm] 704fc65 - [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (#136600)   via llvm-commits
• [llvm] [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (PR #136600)   Craig Topper via llvm-commits
• [llvm] [SelectionDAG] Prefer to use ATOMIC_LOAD extension type over getExtendForAtomicOps() in computeKnownBits/ComputeNumSignBits. (PR #136600)   Craig Topper via llvm-commits
• [flang] [llvm] [flang][openacc] Make async clause behavior homogenous (PR #136610)   via llvm-commits
• [flang] [llvm] [flang][openacc] Make async clause behavior homogenous (PR #136610)   via llvm-commits
• [llvm] [PowerPC] Intrinsics and tests for dmr insert/extract (PR #135653)   via llvm-commits
• [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)   Michael Buch via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)   via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Eli Friedman via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [SeparateConstOffsetFromGEP] Decompose constant xor operand if possible (PR #135788)   Sumanth Gundapaneni via llvm-commits
• [llvm] [SeparateConstOffsetFromGEP] Decompose constant xor operand if possible (PR #135788)   Sumanth Gundapaneni via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [llvm] Use llvm::less_first and llvm::less_second (NFC) (PR #136272)   Kazu Hirata via llvm-commits
• [llvm] [DirectX] Implement the ForwardHandleAccesses pass (PR #135378)   Chris B via llvm-commits
• [llvm] aa5cdc0 - [msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (#136260)   via llvm-commits
• [llvm] [msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (PR #136260)   Thurston Dang via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   Artem Belevich via llvm-commits
• [llvm] [llvm] Use llvm::less_first and llvm::less_second (NFC) (PR #136272)   Kazu Hirata via llvm-commits
• [llvm] [mlir][SMT] update Bazel configuration to match 697aa99 (PR #136616)   via llvm-commits
• [llvm] [mlir][SMT] update Bazel configuration to match 697aa99 (PR #136616)   via llvm-commits
• [flang] [llvm] [flang][openacc] Make async clause behavior homogenous (PR #136610)   Erich Keane via llvm-commits
• [llvm] [NVPTX] add test case for vector reduction intrinsics (PR #136381)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] add test case for vector reduction intrinsics (PR #136381)   Artem Belevich via llvm-commits
• [llvm] [mlir][SMT] update Bazel configuration to match 697aa99 (PR #136616)   Pranav Kant via llvm-commits
• [llvm] [llvm] Construct SmallVector with iterator ranges (NFC) (PR #136460)   Kazu Hirata via llvm-commits
• [clang] [llvm] [Clang][C++23] Core language changes from P1467R9 extended floating-point types and standard names. (PR #78503)   Shafik Yaghmour via llvm-commits
• [llvm] [msan][NFCI] Add avx512fp16-{arith-intrinsics, arith-vl-intrinsics, intrinsics} tests (PR #136260)   LLVM Continuous Integration via llvm-commits
• [llvm] [SeparateConstOffsetFromGEP] Decompose constant xor operand if possible (PR #135788)   Sumanth Gundapaneni via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Jakub Kuderski via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Kazu Hirata via llvm-commits
• [llvm] [mlir][SMT] update Bazel configuration to match 697aa99 (PR #136616)   Pranav Kant via llvm-commits
• [llvm] [mlir][SMT] update Bazel configuration to match 697aa99 (PR #136616)   via llvm-commits
• [llvm] [SystemZ] Handle f16 load positive/negative/complement without libcalls. (PR #136286)   Trevor Gross via llvm-commits
• [llvm] [PowerPC] Intrinsics and tests for dmr insert/extract (PR #135653)   Maryam Moghadas via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   Simon Pilgrim via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   via llvm-commits
• [llvm] a945f59 - AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (#136609)   via llvm-commits
• [llvm] AMDGPU: Add global-isel checks and rename fptrunc.v2f16.fpmath.ll (PR #136609)   Changpeng Fang via llvm-commits
• [llvm] [msan] Handle x86.avx512fp16.{add, sub.mul, div, min, max}.ph.512 (PR #136619)   Thurston Dang via llvm-commits
• [llvm] [msan] Handle x86.avx512fp16.{add, sub.mul, div, min, max}.ph.512 (PR #136619)   via llvm-commits
• [llvm] [msan] Handle x86.avx512fp16.{add, sub.mul, div, min, max}.ph.512 (PR #136619)   via llvm-commits
• [llvm] [PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (PR #133109)   Maryam Moghadas via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   Alan Phipps via llvm-commits
• [llvm] [PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (PR #133109)   Maryam Moghadas via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   Craig Topper via llvm-commits
• [llvm] 3ceb3d9 - [flang][openacc] Make async clause behavior homogenous (#136610)   via llvm-commits
• [flang] [llvm] [flang][openacc] Make async clause behavior homogenous (PR #136610)   Valentin Clement バレンタイン クレメン via llvm-commits
• [llvm] [mlir] Emitc.convert (PR #136621)   Mircea Trofin via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [mlir] Emitc.convert (PR #136621)   via llvm-commits
• [llvm] [mlir] Emitc.convert (PR #136621)   via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Jakub Kuderski via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Jakub Kuderski via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Kazu Hirata via llvm-commits
• [llvm] 515564a - [AMDGPU] Partially revert my llvm::less_second patch (#136615)   via llvm-commits
• [llvm] [AMDGPU] Partially revert my llvm::less_second patch (PR #136615)   Kazu Hirata via llvm-commits
• [llvm] [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (PR #136622)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (PR #136622)   via llvm-commits
• [clang] [llvm] Add support for flag output operand "=@cc" for SystemZ. (PR #125970)   via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Analysis for DLL export (PR #136623)   Andrew Rogers via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Snehasish Kumar via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Analysis for DLL export (PR #136623)   via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Analysis for DLL export (PR #136623)   Andrew Rogers via llvm-commits
• [llvm] [llvm] revisions to export annotation macros to avoid compiler warnings (PR #135995)   Andrew Rogers via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Artem Belevich via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Artem Belevich via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Artem Belevich via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [lld] 8389d6f - [lld] Merge equivalent symbols found during ICF (#134342)   via llvm-commits
• [lld] [lld] Merge equivalent symbols found during ICF (PR #134342)   Pranav Kant via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [llvm] [NVPTX] Improve kernel byval parameter lowering (PR #136008)   Artem Belevich via llvm-commits
• [llvm] 92c0b42 - [NVPTX] add test case for vector reduction intrinsics (#136381)   via llvm-commits
• [llvm] [NVPTX] add test case for vector reduction intrinsics (PR #136381)   Princeton Ferro via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect their implementation (PR #136625)   Pranav Kant via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect their implementation (PR #136625)   via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect their implementation (PR #136625)   via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect their implementation (PR #136625)   via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect their implementation (PR #136625)   Pranav Kant via llvm-commits
• [lld] [lld] NFC. Rename function to better reflect its implementation (PR #136625)   Pranav Kant via llvm-commits
• [lld] [lld] Merge equivalent symbols found during ICF (PR #134342)   Pranav Kant via llvm-commits
• [llvm] [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (PR #136622)   Chris B via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (PR #136622)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (PR #136622)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] c40d3a4 - [PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (#133109)   via llvm-commits
• [llvm] [PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions (PR #133109)   Maryam Moghadas via llvm-commits
• [llvm] [PowerPC] Add dense math half-precision floating-point outer-product accumulate to DMR instructions (PR #133272)   Maryam Moghadas via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Alex MacLean via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] legalize memset (PR #136244)   Farzon Lotfi via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/ADT for DLL export (PR #136629)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/ADT for DLL export (PR #136629)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/ADT for DLL export (PR #136629)   Andrew Rogers via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/Analysis for DLL export (PR #136623)   Andrew Rogers via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/ADT for DLL export (PR #136629)   via llvm-commits
• [llvm] [llvm] annotate interfaces in llvm/ADT for DLL export (PR #136629)   Andrew Rogers via llvm-commits
• [llvm] [NVPTX] Improve kernel byval parameter lowering (PR #136008)   Alex MacLean via llvm-commits
• [llvm] 56910a8 - [NVPTX] Improve kernel byval parameter lowering (#136008)   via llvm-commits
• [llvm] [NVPTX] Improve kernel byval parameter lowering (PR #136008)   Alex MacLean via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Durgadoss R via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   via llvm-commits
• [clang] [llvm] Add support for flag output operand "=@cc" for SystemZ. (PR #125970)   via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Adam Yang via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   Rahul Joshi via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   Eli Friedman via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   Peter Collingbourne via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   Peter Collingbourne via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Saleem Abdulrasool via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   LLVM Continuous Integration via llvm-commits
• [llvm] [LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (PR #136632)   Rahul Joshi via llvm-commits
• [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)   Rahul Joshi via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Shilei Tian via llvm-commits
• [llvm] [llvm] Ensure propagated constants in the vtable are aligned (PR #136630)   via llvm-commits
• [llvm] [AA] Move Target Specific AA before BasicAA (PR #125965)   via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Elvis Wang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [msan] Handle x86.avx512fp16.{add, sub.mul, div, min, max}.ph.512 (PR #136619)   Florian Mayer via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Steve O'Brien via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [LV]Enable non-power-of-2 store-load forwarding distance in predicated DataWithEVL vectorization mode (PR #100755)   Alexey Bataev via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [compiler-rt] 53e62c6 - [compiler-rt][profile][tests][NFC] Avoid using a.out from PATH (#136465)   via llvm-commits
• [compiler-rt] [compiler-rt][profile][tests][NFC] Avoid using a.out from PATH (PR #136465)   Hubert Tong via llvm-commits
• [llvm] d2fedd6 - [NVPTX] mark unused variable introduced by 56910a8b1b302ebf37e9d30bd200091fd23dc232 [NFC]   Augie Fackler via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] d1f4f52 - [msan] Handle x86.avx512fp16.{add,sub.mul,div,min,max}.ph.512 (#136619)   via llvm-commits
• [llvm] [msan] Handle x86.avx512fp16.{add, sub.mul, div, min, max}.ph.512 (PR #136619)   Thurston Dang via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] a1db2c6 - [RISCV] Remove duplicate call to MFI.getStackID(FI). NFC   Craig Topper via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Artem Belevich via llvm-commits
• [llvm] 2cdf474 - [MemProf] Merge callee clones as needed before assigning functions (#135702)   via llvm-commits
• [llvm] [MemProf] Merge callee clones as needed before assigning functions (PR #135702)   Teresa Johnson via llvm-commits
• [llvm] [llvm] add LLVM_FRIEND_ABI macro for friend function decls (PR #136595)   Andrew Rogers via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   Mateusz Mikuła via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] [LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (PR #136632)   Min-Yih Hsu via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   YunQiang Su via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Florian Mayer via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   YunQiang Su via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] [AMDGPU] Enable vectorization of i8 values. (PR #134934)   Jeffrey Byrnes via llvm-commits
• [llvm] LowerTypeTests: Switch to emitting one inline asm call per jump table entry. (PR #136265)   Florian Mayer via llvm-commits
• [llvm] LowerTypeTests: Switch to emitting one inline asm call per jump table entry. (PR #136265)   Florian Mayer via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   zhijian lin via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   via llvm-commits
• [llvm] LowerTypeTests: Switch to emitting one inline asm call per jump table entry. (PR #136265)   Peter Collingbourne via llvm-commits
• [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)   zhijian lin via llvm-commits
• [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)   YunQiang Su via llvm-commits
• [llvm] [LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (PR #136632)   Rahul Joshi via llvm-commits
• [llvm] 2b44eb9 - [LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (#136632)   via llvm-commits
• [llvm] [LLVM][TableGen] Fix VarlenDecoder.td to not used fixed opcode values (PR #136632)   Rahul Joshi via llvm-commits
• [llvm] SelectionDAG: Fix isKnownNeverNaN for Min and Max (PR #135742)   YunQiang Su via llvm-commits
• [llvm] SelectionDAG: Fix isKnownNeverNaN for Min and Max (PR #135742)   YunQiang Su via llvm-commits
• [llvm] c7ea01b - LowerTypeTests: Switch to emitting one inline asm call per jump table entry.   via llvm-commits
• [llvm] LowerTypeTests: Switch to emitting one inline asm call per jump table entry. (PR #136265)   Peter Collingbourne via llvm-commits
• [llvm] PowerPC/VSX: Select FMINNUM and FMAXNUM (PR #135739)   YunQiang Su via llvm-commits
• [clang] [llvm] [WIP] Correct lowering of `fp128` intrinsics (PR #76558)   Trevor Gross via llvm-commits
• [llvm] RISC-V: Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (PR #135727)   YunQiang Su via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   Alex MacLean via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   via llvm-commits
• [llvm] LowerTypeTests: Switch to emitting one inline asm call per jump table entry. (PR #136265)   Vitaly Buka via llvm-commits
• [llvm] [NVPTX] Use v2.u64 to load/store 128-bit values (PR #136638)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Use v2.u64 to load/store 128-bit values (PR #136638)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Use v2.u64 to load/store 128-bit values (PR #136638)   via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [clang] [llvm] [TargetVerifier][AMDGPU] Add TargetVerifier. (PR #123609)   Shilei Tian via llvm-commits
• [llvm] RISC-V: Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (PR #135727)   YunQiang Su via llvm-commits
• [llvm] 698cd48 - [RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287)   via llvm-commits
• [llvm] [RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (PR #136287)   Jim Lin via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   Princeton Ferro via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   via llvm-commits
• [llvm] ddb8870 - [RISCV] Remove the FIXME for using sraiw+and. NFC.   Jim Lin via llvm-commits
• [llvm] Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (PR #136475)   via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [llvm] [NVPTX] Use v2.u64 to load/store 128-bit values (PR #136638)   Alex MacLean via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [llvm] [NVPTX] Use v2.u64 to load/store 128-bit values (PR #136638)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Jim Lin via llvm-commits
• [lld] WIP --- [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [ConstraintElim] Add facts about non-poison intrinsics on demand (PR #136558)   Yingwei Zheng via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] SelectionDAG: Fix isKnownNeverNaN for Min and Max (PR #135742)   YunQiang Su via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [lldb][LoongArch] Fix expression function call failure (PR #136563)   Lu Weining via llvm-commits
• [llvm] PowerPC/VSX: Select FMINNUM and FMAXNUM (PR #135739)   YunQiang Su via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [lld] WIP --- [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [lld] [lld][ICF] Prevent merging two sections when they point to non-globals (PR #136641)   Pranav Kant via llvm-commits
• [lld] [lld] Merge equivalent symbols found during ICF (PR #134342)   Pranav Kant via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (PR #135925)   Ikhlas Ajbar via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (PR #135925)   Ikhlas Ajbar via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Ws lend (PR #136643)   via llvm-commits
• [llvm] Ws lend (PR #136643)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [TTI] Make all interface methods const (PR #136598)   Sergei Barannikov via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [TTI] Make all interface methods const (NFCI) (PR #136598)   Sergei Barannikov via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [lldb][LoongArch] Fix expression function call failure (PR #136563)   via llvm-commits
• [llvm] Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (PR #136475)   Sergei Barannikov via llvm-commits
• [llvm] [lldb][LoongArch] Fix expression function call failure (PR #136563)   via llvm-commits
• [llvm] [InstCombine] Preserve signbit semantics of NaN with fold to fabs (PR #136648)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Preserve signbit semantics of NaN with fold to fabs (PR #136648)   via llvm-commits
• [llvm] 0014b49 - [TTI] Make all interface methods const (NFCI) (#136598)   via llvm-commits
• [llvm] [TTI] Make all interface methods const (NFCI) (PR #136598)   Sergei Barannikov via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Liao Chunyu via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [llvm] [LLVM] Pass correct target to LLVM_RUNTIMES_TARGET for runtimes (PR #136572)   Joseph Huber via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Joseph Huber via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   Shilei Tian via llvm-commits
• [llvm] [SLP]Prefer segmented/deinterleaved loads to strided and fix codegen (PR #135058)   via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Marius Kamp via llvm-commits
• [llvm] [X86] Distribute Certain Bitwise Operations over SELECT (PR #136555)   Marius Kamp via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Marius Kamp via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)   Marius Kamp via llvm-commits
• [llvm] [InstCombine] Preserve signbit semantics of NaN with fold to fabs (PR #136648)   Yingwei Zheng via llvm-commits
• [llvm] [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (PR #136651)   Craig Topper via llvm-commits
• [llvm] [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (PR #136651)   via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)   Shilei Tian via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Craig Topper via llvm-commits
• [llvm] 9e26c79 - [RISCV] Add smcntrpmf extension (#136556)   via llvm-commits
• [clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)   Liao Chunyu via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Shilei Tian via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (PR #136651)   Sergei Barannikov via llvm-commits
• [llvm] [X86][SelectionDAG] Fix the Gather's base and index by modifying the Scale value (PR #134979)   Rohit Aggarwal via llvm-commits
• [llvm] [LLVM][Cygwin] Fix llvm-config shared library names (PR #136599)   via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Petr Hosek via llvm-commits
• [libc] [llvm] [LLVM] Replace use of `LLVM_RUNTIMES_TARGET` with `LLVM_DEFAULT_TARGET_TRIPLE` (PR #136208)   Petr Hosek via llvm-commits
• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   Princeton Ferro via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   Princeton Ferro via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [lldb][LoongArch] Fix expression function call failure (PR #136563)   Lu Weining via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)   Christudasan Devadasan via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)   Christudasan Devadasan via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   Durgadoss R via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [NVPTX] Add support for PTX ISA v8.8 (PR #136639)   Durgadoss R via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] 497382e - [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (#136651)   via llvm-commits
• [llvm] [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (PR #136651)   Craig Topper via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   Craig Topper via llvm-commits
• [llvm] [CodeGen][NPM] Do not add required passes to pipeline (PR #135752)   Akshat Oke via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)   via llvm-commits
• [llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)   via llvm-commits
• [llvm] [CodeGen][NPM] Do not add required passes to pipeline (PR #135752)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM] Do not add required passes to pipeline (PR #135752)   via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   Craig Topper via llvm-commits
• [llvm] [InstCombine] fold u <= (u <= (unsigned)b) into (u <= (unsigned)b). (PR #136654)   via llvm-commits
• [llvm] [InstCombine] fold u <= (u <= (unsigned)b) into (u <= (unsigned)b). (PR #136654)   via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)   Thurston Dang via llvm-commits
• [llvm] [CodeGen][NPM] Support generic regalloc-npm option (PR #135149)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM] Support generic regalloc-npm option (PR #135149)   Akshat Oke via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space. (PR #135444)   via llvm-commits
• [llvm] [CodeGen][NPM] Support generic regalloc-npm option (PR #135149)   Akshat Oke via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Fix discrepancies between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] [AMDGPU] Do not fold COPY with implicit operands (PR #136003)   Mariusz Sikora via llvm-commits
• [llvm] [AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (PR #134629)   Frederik Harwath via llvm-commits
• [llvm] [SelectionDAG] Make the FoldingSet profile in getAtomic match AddNodeIDCustom. (PR #136651)   LLVM Continuous Integration via llvm-commits
• [llvm] [TTI] Fix discrepancies between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   via llvm-commits
• [llvm] [CodeGen][NPM] Support generic regalloc-npm option (PR #135149)   Akshat Oke via llvm-commits
• [llvm] [NVPTX] Add mix precision arith intrinsics (PR #136657)   Rajat Bajpai via llvm-commits
• [llvm] [CodeGen][NPM] Support generic regalloc-npm option (PR #135149)   Akshat Oke via llvm-commits
• [llvm] [NVPTX] Add mix precision arith intrinsics (PR #136657)   via llvm-commits
• [llvm] [NVPTX] Add mix precision arith intrinsics (PR #136657)   Rajat Bajpai via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   Phoebe Wang via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   Matt Arsenault via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   Phoebe Wang via llvm-commits
• [llvm] 784dc16 - [LangRef][IR] Fix default AS documentation for allocas without explicit AS (#135942)   via llvm-commits
• [llvm] [LangRef][IR] Fix default AS documentation for allocas without explicit AS (PR #135942)   Fabian Ritter via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   Sudharsan Veeravalli via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   Phoebe Wang via llvm-commits
• [llvm] [CodeGen][NPM] Do not add required passes to pipeline (PR #135752)   Akshat Oke via llvm-commits
• [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)   Hristo Hristov via llvm-commits
• [llvm] [SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (PR #136653)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Stanislav Mekhanoshin via llvm-commits
• [clang] [lld] [llvm] [X86] Implement disabling APX relocations and EPGR/NDD instrs for relocations (PR #136660)   Feng Zou via llvm-commits
• [clang] [lld] [llvm] [X86] Implement disabling APX relocations and EPGR/NDD instrs for relocations (PR #136660)   via llvm-commits
• [clang] [lld] [llvm] [X86] Implement disabling APX relocations and EPGR/NDD instrs for relocations (PR #136660)   via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   Phoebe Wang via llvm-commits
• [llvm] [NVPTX] Add fma mix precision intrinsics (PR #136661)   Rajat Bajpai via llvm-commits
• [llvm] [NVPTX] Add fma mix precision intrinsics (PR #136661)   Rajat Bajpai via llvm-commits
• [llvm] [NVPTX] Add fma mix precision intrinsics (PR #136661)   via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #136631)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   via llvm-commits
• [llvm] [LoopUtils] Cache VFs in addDiffRuntimeChecks (NFC) (PR #130157)   Ramkumar Ramachandra via llvm-commits
• [llvm] [LV] Use requested calling convention for vector math routines (PR #136122)   David Sherwood via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   via llvm-commits
• [llvm] [LV] Use requested calling convention for vector math routines (PR #136122)   David Sherwood via llvm-commits
• [llvm] [InstCombine] Fix ninf propagation for fcmp+sel -> minmax (PR #136433)   Yingwei Zheng via llvm-commits
• [clang] [llvm] [Clang] [OpenMP] Support NOWAIT with optional argument (PR #135030)   via llvm-commits
• [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)   Fabian Ritter via llvm-commits
• [clang] [llvm] [Clang] [OpenMP] Support NOWAIT with optional argument (PR #128742)   via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Pankaj Dwivedi via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Luke Lau via llvm-commits
• [llvm] [GlobalISel] Add `combine` action for C++ combine rules (PR #135941)   Pierre van Houtryve via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Luke Lau via llvm-commits
• [llvm] [GlobalISel] Diagnose inline assembly constraint lowering errors (PR #135782)   Pierre van Houtryve via llvm-commits
• [llvm] [AMDGPU][SplitModule] Do not create empty modules (PR #135761)   Pierre van Houtryve via llvm-commits
• [clang] [lld] [llvm] [X86] Implement disabling APX relocations and EPGR/NDD instrs for relocations (PR #136660)   Shengchen Kan via llvm-commits
• [llvm] [GlobalISel] Add `combine` action for C++ combine rules (PR #135941)   Pierre van Houtryve via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Luke Lau via llvm-commits
• [llvm] [GlobalISel] Add `combine` action for C++ combine rules (PR #135941)   Pierre van Houtryve via llvm-commits
• [llvm] [BOLT][binary-analysis] Fix pac-ret scanner's "major limitation" (PR #136664)   Gergely Bálint via llvm-commits
• [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)   Luke Lau via llvm-commits
• [llvm] [BOLT][binary-analysis] Fix pac-ret scanner's "major limitation" (PR #136664)   via llvm-commits
• [llvm] [BOLT][binary-analysis] Fix pac-ret scanner's "major limitation" (PR #136664)   Gergely Bálint via llvm-commits
• [llvm] [BOLT][binary-analysis] Fix pac-ret scanner's "major limitation" (PR #136664)   via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   Luke Lau via llvm-commits
• [llvm] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Paschalis Mpeis via llvm-commits
• [llvm] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)   Luke Lau via llvm-commits
• [llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)   Princeton Ferro via llvm-commits
• [llvm] [SPIR-V] Fix OpVectorShuffle operands on load (PR #135954)   Nathan Gauër via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)   via llvm-commits
• [llvm] [mlir] [mlir][gpu] Change GPU modules to globals (PR #135478)   Christian Sigg via llvm-commits
• [clang] [lld] [llvm] [X86] Implement disabling APX relocations and EPGR/NDD instrs for relocations (PR #136660)   Feng Zou via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] [IR] Relax convergence requirements on call (PR #135794)   Nathan Gauër via llvm-commits
• [llvm] [IR] Relax convergence requirements on call (PR #135794)   Nathan Gauër via llvm-commits
• [llvm] Clarify conditions of `lit` exiting with exit code 1 (PR #136190)   James Henderson via llvm-commits
• [llvm] f541a3a - [AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (#134629)   via llvm-commits
• [llvm] [AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (PR #134629)   Frederik Harwath via llvm-commits
• [llvm] [IR] Relax convergence requirements on call (PR #135794)   Sameer Sahasrabuddhe via llvm-commits
• [llvm] [TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (PR #136668)   Sergei Barannikov via llvm-commits
• [llvm] [TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (PR #136668)   via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)   Matt Arsenault via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Matt Arsenault via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Matt Arsenault via llvm-commits
• [llvm] [NFC] Fixed test case fail caused by the patch [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode #122741 (PR #136636)   Matt Arsenault via llvm-commits
• [clang] [llvm] reduce max wrt divergent mask (PR #135138)   Aniket Lal via llvm-commits
• [llvm] Reland "[LoopVectorizer] Add support for chaining partial reductions #120272" (PR #124282)   Mikael Holmén via llvm-commits
• [llvm] [SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (PR #135225)   Vyacheslav Levytskyy via llvm-commits
• [clang] [llvm] reduce over divergent mask (PR #133228)   Aniket Lal via llvm-commits
• [llvm] ef72b93 - [LV] Use requested calling convention for vector math routines (#136122)   via llvm-commits
• [llvm] [LV] Use requested calling convention for vector math routines (PR #136122)   David Sherwood via llvm-commits
• [clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)   Jim Lin via llvm-commits
• [clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)   via llvm-commits
• [clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)   via llvm-commits
• [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)   via llvm-commits
• [llvm] [SystemZ] Handle f16 load positive/negative/complement without libcalls. (PR #136286)   Ulrich Weigand via llvm-commits
• [llvm] [SystemZ] Handle f16 load positive/negative/complement without libcalls. (PR #136286)   Ulrich Weigand via llvm-commits
• [llvm] [SystemZ] Handle f16 load positive/negative/complement without libcalls. (PR #136286)   Ulrich Weigand via llvm-commits
• [llvm] [SystemZ] Handle f16 load positive/negative/complement without libcalls. (PR #136286)   Ulrich Weigand via llvm-commits
• [llvm] 3334c35 - [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (#136655)   via llvm-commits
• [llvm] [TTI] Fix discrepancies in prototypes between interface and implementations (NFCI) (PR #136655)   Sergei Barannikov via llvm-commits
• [llvm] c3f815b - Modify the localCache API to require an explicit commit on CachedFile… (#136121)   via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #136121)   via llvm-commits
• [llvm] [SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. (PR #136131)   Ulrich Weigand via llvm-commits
• [llvm] [SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. (PR #136131)   Ulrich Weigand via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)   Sam Elliott via llvm-commits
• [llvm] 278c429 - [ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)   Nikita Popov via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)   Florian Hahn via llvm-commits
• [llvm] [InstCombine] Do not combine shuffle+bitcast if the bitcast is eliminable. (PR #135769)   Ricardo Jesus via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (PR #135056)   Martin Storsjö via llvm-commits
• [llvm] [InstCombine] Do not combine shuffle+bitcast if the bitcast is eliminable. (PR #135769)   Nikita Popov via llvm-commits
• [llvm] [DWARFLinker] Update `stmt-seq-macho.test` to use `update_test_body.py` (PR #133363)   Ulrich Weigand via llvm-commits
• [llvm] [SPIR-V] Add store legalization for ptrcast (PR #135369)   Nathan Gauër via llvm-commits
• [llvm] [InstCombine] fold u <= (u <= (unsigned)b) into (u <= (unsigned)b). (PR #136654)   Yingwei Zheng via llvm-commits
• [llvm] d8b0e61 - [SPIR-V] Fix OpVectorShuffle operands on load (#135954)   via llvm-commits
• [llvm] [SPIR-V] Fix OpVectorShuffle operands on load (PR #135954)   Nathan Gauër via llvm-commits
• [llvm] [SPIR-V] Add store legalization for ptrcast (PR #135369)   Nathan Gauër via llvm-commits
• [clang] [llvm] [ARM] Adding diagnostics for mcmodel=tiny when used in invalid targets (PR #125643)   via llvm-commits
• [llvm] [X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector (PR #135010)   Rohit Aggarwal via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)   Florian Hahn via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   Simon Pilgrim via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] Stitch up loop passes in codegen pipeline (PR #133050)   Akshat Oke via llvm-commits
• [llvm] [X86] SimplifyDemandedBitsForTargetNode - add handling for X86ISD::FAND/FOR (PR #136618)   Simon Pilgrim via llvm-commits
• [llvm] Stitch up loop passes in codegen pipeline (PR #133050)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM]Stitch up loop passes in codegen pipeline (PR #133050)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM]Stitch up loop passes in codegen pipeline (PR #133050)   via llvm-commits
• [llvm] [SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (PR #135225)   Dmitry Sidorov via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #133050)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #133050)   Akshat Oke via llvm-commits
• [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)   Simon Pilgrim via llvm-commits
• [clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)   Alex Voicu via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)   Gergely Bálint via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #136121)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)   Djordje Todorovic via llvm-commits
• [clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)   Djordje Todorovic via llvm-commits
• [llvm] [AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (PR #134629)   LLVM Continuous Integration via llvm-commits
• [llvm] [HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (PR #135925)   Abinaya Saravanan via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits
• [clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)   Dmitry Sidorov via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   Yingwei Zheng via llvm-commits
• [llvm] 9efd798 - [TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (#136668)   via llvm-commits
• [llvm] [TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC) (PR #136668)   Sergei Barannikov via llvm-commits
• [clang] [llvm] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and scalable vectors. (PR #130973)   Paul Walker via llvm-commits
• [llvm] [TTI] Simplify implementation (NFCI) (PR #136674)   Sergei Barannikov via llvm-commits
• [llvm] [InstCombine] Canonicalize `smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)` (PR #136665)   via llvm-commits

Last message date: Tue Apr 22 02:54:47 PDT 2025
Archived on: Tue Apr 22 02:54:50 PDT 2025

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