[llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)

[via llvm-commits]

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@@ -1068,6 +1068,20 @@ void SIFoldOperandsImpl::foldOperand(
     if (MovOp == AMDGPU::COPY)
       return;
 
+    // Check for common register subclass between destination (DestRC) and MOV
+    // result (ResRC). If exists, verify this common subclass is a superclass of
+    // (or equal to) the destination register class, otherwise folding is
+    // illegal.
+
+    const MCInstrDesc &MovDesc = TII->get(MovOp);
+    assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
+    const TargetRegisterClass *ResRC =
+        TRI->getRegClass(MovDesc.operands()[0].RegClass);
+    const TargetRegisterClass *CommonRC = TRI->getCommonSubClass(DestRC, ResRC);
+
+    if (!CommonRC || !DestRC->hasSuperClassEq(CommonRC))
+      return;
+
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mssefat wrote:


I think hasSuperClassEq is not redundant with finding common subclass. Consider this basic block where the copy operation is illegal:

bb.0:
  %1:av_32 = V_MOV_B32_e32 32, implicit $exec
  $agpr0 = COPY %1:av_32
  S_ENDPGM 0

In this example:

DestRC is AV_32
ResRC is VGPR_32
CommonRC is VGPR_32

If we only check for CommonRC, the check would allow folding in this case since CommonRC exists (VGPR_32). However, folding here is illegal. And I think we need the condition if ( !DestRC->hasSuperClassEq(CommonRC) return.

https://github.com/llvm/llvm-project/pull/131387