[llvm] [IVDescriptors] Don't require nsz/nnan for (min|max)num. (PR #137003)

[Florian Hahn via llvm-commits]

fhahn wrote:

> Yeah - My understanding was that the behaviour of fmax in glibc is equivalent to maxnum, which is equivalent to fmaxnm. So the patch in #112852 brought the documentation in line how it always worked for AArch64/Arm, and what fmax should always have produced. It would certainly be nice for min/max reductions to vectorize without nonan, but generating 3 instructions for every fmin/fmax would be a shame too. (Hopefully some of them can detect no-snan from the generating instruction and not hit the issue, but it likely won't help everywhere).

I guess the question is if there's anything we could do to still match GCC's behavior? It would indeed be a shame if we would have to generate more instructions than gcc ;) 

For the vector-reduction case, we will need to generate one extra op to silence the NaN, as the reduction value is guaranteed no-snan, if the start value isnt' snan.

https://github.com/llvm/llvm-project/pull/137003