[llvm] [AArch64][SVE] Generate asrd instruction for positive pow-2 divisors … (PR #137151)

[Sushant Gokhale via llvm-commits]

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@@ -18421,6 +18421,11 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
 
   EVT VT = N->getValueType(0);
 
+  // For negative divisor, this yeilds (ptrue + asrd + subr) which is not
+  // profitable as compared to Neon sequence (cmlt + usra + sshr).
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sushgokh wrote:

done

https://github.com/llvm/llvm-project/pull/137151