[llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (PR #132381)

[Matt Arsenault via llvm-commits]

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@@ -127,6 +131,120 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy,
   MI.eraseFromParent();
 }
 
+bool isSignedBFE(MachineInstr &MI) {
+  if (isa<GIntrinsic>(MI)) {
+    switch (MI.getOperand(1).getIntrinsicID()) {
+    case Intrinsic::amdgcn_sbfe:
+      return true;
+    case Intrinsic::amdgcn_ubfe:
+      return false;
+    default:
+      llvm_unreachable("Opcode not supported");
+    }
+  } else {
+    switch (MI.getOpcode()) {
+    case AMDGPU::G_SBFX:
+      return true;
+    case AMDGPU::G_UBFX:
+      return false;
+    default:
+      llvm_unreachable("Opcode not supported");
+    }
+  }
+}
+
+void RegBankLegalizeHelper::lowerDiv_BFE(MachineInstr &MI) {
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arsenm wrote:

"Div" may be confused with division. This also isn't really about divergence, but VGPR. lowerV_BFE?

https://github.com/llvm/llvm-project/pull/132381