[llvm] [RISCV] Add scheduler definitions for SpacemiT-X60 (PR #137343)

[Min-Yih Hsu via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva22u64 -mcpu=spacemit-x60 -iterations=1 < %s | FileCheck %s
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mshockwave wrote:

I don't think you need `-mattr` here, the CPU definition should already specify all the extensions

https://github.com/llvm/llvm-project/pull/137343