[llvm] [Mips] Support "$sp" named register (PR #136821)

[via llvm-commits]

https://github.com/yingopq created https://github.com/llvm/llvm-project/pull/136821

Fix #47656.

>From 11d66917411a3522c59ba9694352c4018646b4d2 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Tue, 22 Apr 2025 22:29:52 -0400
Subject: [PATCH] [Mips] Support "$sp" named register

Fix #47656.
---
 llvm/lib/Target/Mips/MipsISelLowering.cpp    |  2 ++
 llvm/test/CodeGen/Mips/named-register-n32.ll | 11 +++++++++++
 llvm/test/CodeGen/Mips/named-register-n64.ll | 11 +++++++++++
 llvm/test/CodeGen/Mips/named-register-o32.ll | 11 +++++++++++
 4 files changed, 35 insertions(+)

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index bd65431b475d0..deb9f1a6daac4 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4898,6 +4898,7 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
     Register Reg = StringSwitch<Register>(RegName)
                        .Case("$28", Mips::GP_64)
                        .Case("sp", Mips::SP_64)
+                       .Case("$sp", Mips::SP_64)
                        .Default(Register());
     if (Reg)
       return Reg;
@@ -4905,6 +4906,7 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
     Register Reg = StringSwitch<Register>(RegName)
                        .Case("$28", Mips::GP)
                        .Case("sp", Mips::SP)
+                       .Case("$sp", Mips::SP)
                        .Default(Register());
     if (Reg)
       return Reg;
diff --git a/llvm/test/CodeGen/Mips/named-register-n32.ll b/llvm/test/CodeGen/Mips/named-register-n32.ll
index 112e04e14b2ac..83bd437a96085 100644
--- a/llvm/test/CodeGen/Mips/named-register-n32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n32.ll
@@ -22,8 +22,19 @@ define i64 @get_sp() {
   ret i64 %1
 }
 
+define i64 @get_$sp() {
+; CHECK-LABEL: get_$sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !2)
+  ret i64 %1
+}
+
 !llvm.named.register.$28 = !{!0}
 !llvm.named.register.sp = !{!1}
+!llvm.named.register.$sp = !{!2}
 
 !0 = !{!"$28"}
 !1 = !{!"sp"}
+!2 = !{!"$sp"}
diff --git a/llvm/test/CodeGen/Mips/named-register-n64.ll b/llvm/test/CodeGen/Mips/named-register-n64.ll
index 42d9ba1e1f15c..c0e9f75418485 100644
--- a/llvm/test/CodeGen/Mips/named-register-n64.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n64.ll
@@ -22,8 +22,19 @@ define i64 @get_sp() {
   ret i64 %1
 }
 
+define i64 @get_$sp() {
+; CHECK-LABEL: get_$sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !2)
+  ret i64 %1
+}
+
 !llvm.named.register.$28 = !{!0}
 !llvm.named.register.sp = !{!1}
+!llvm.named.register.$sp = !{!2}
 
 !0 = !{!"$28"}
 !1 = !{!"sp"}
+!2 = !{!"$sp"}
diff --git a/llvm/test/CodeGen/Mips/named-register-o32.ll b/llvm/test/CodeGen/Mips/named-register-o32.ll
index 280c56e4db6a4..74cbcd2d739d8 100644
--- a/llvm/test/CodeGen/Mips/named-register-o32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-o32.ll
@@ -22,8 +22,19 @@ define i32 @get_sp() {
   ret i32 %1
 }
 
+define i32 @get_$sp() {
+; CHECK-LABEL: get_$sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %1
+}
+
 !llvm.named.register.$28 = !{!0}
 !llvm.named.register.sp = !{!1}
+!llvm.named.register.$sp = !{!2}
 
 !0 = !{!"$28"}
 !1 = !{!"sp"}
+!2 = !{!"$sp"}