[llvm] [TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (PR #137096)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 24 08:27:45 PDT 2025

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/137096

Previous message: [llvm] [TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (PR #137096)
Next message: [llvm] [Dwarf] Emit `DW_AT_bit_size` for non-byte-sized types (PR #137118)
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