[llvm] [RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (PR #136799)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/136799

The Zalasr load/store don't support reg-imm addressing modes so they
can't fold an ADDI.

>From dcfe7d4e1aafa4064eedd6ca335d8ddc7ead06a5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 22 Apr 2025 19:27:10 -0700
Subject: [PATCH 1/2] Pre-commit test case

---
 .../CodeGen/RISCV/zalasr-offset-folding.ll    | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll

diff --git a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
new file mode 100644
index 0000000000000..8902c2e497bd0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+experimental-zalasr | FileCheck %s
+
+; FIXME: We should not fold -1920 into the lw instruction because we still
+; need it for the sw.rl.
+
+define i32 @test(ptr %p) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, 20
+; CHECK-NEXT:    add a2, a0, a1
+; CHECK-NEXT:    addi a1, a1, -1920
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sw.rl a1, (a0)
+; CHECK-NEXT:    lw a0, -1920(a2)
+; CHECK-NEXT:    ret
+entry:
+  %gep0 = getelementptr [65536 x i32], ptr %p, i64 0, i32 20000
+  store atomic i32 2, ptr %gep0 seq_cst, align 4
+  %a = load i32, ptr %gep0
+  ret i32 %a
+}

>From e972835f0334191ff6874202ce8bf87ffba48268 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 22 Apr 2025 19:28:57 -0700
Subject: [PATCH 2/2] [RISCV] Return false for Zalasr load/store in
 isWorthFoldingAdd.

The Zalasr load/store don't support reg-imm addressing modes so they
can't fold an ADDI.
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp      | 2 ++
 llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll | 5 ++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 4de93d5d5abde..ad77106d386c9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2599,6 +2599,8 @@ static bool isWorthFoldingAdd(SDValue Add) {
     if (User->getOpcode() == ISD::ATOMIC_STORE &&
         cast<AtomicSDNode>(User)->getVal() == Add)
       return false;
+    if (isStrongerThanMonotonic(cast<MemSDNode>(User)->getSuccessOrdering()))
+      return false;
   }
 
   return true;
diff --git a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
index 8902c2e497bd0..78653ba3b78ef 100644
--- a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
+++ b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
@@ -1,19 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+experimental-zalasr | FileCheck %s
 
-; FIXME: We should not fold -1920 into the lw instruction because we still
+; Make sure we don't fold -1920 into the lw instruction because we still
 ; need it for the sw.rl.
 
 define i32 @test(ptr %p) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, 20
-; CHECK-NEXT:    add a2, a0, a1
 ; CHECK-NEXT:    addi a1, a1, -1920
 ; CHECK-NEXT:    add a0, a0, a1
 ; CHECK-NEXT:    li a1, 2
 ; CHECK-NEXT:    sw.rl a1, (a0)
-; CHECK-NEXT:    lw a0, -1920(a2)
+; CHECK-NEXT:    lw a0, 0(a0)
 ; CHECK-NEXT:    ret
 entry:
   %gep0 = getelementptr [65536 x i32], ptr %p, i64 0, i32 20000