[llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)

[Brox Chen via llvm-commits]

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@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            wwm_reg_skip_sort_16bit
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
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broxigarchen wrote:

Hi Christ. Then this is a bug. The shifting is happening for the entry function here https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp#L1658 



https://github.com/llvm/llvm-project/pull/135053