[clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)
Liao Chunyu via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 21 20:36:05 PDT 2025
https://github.com/ChunyuLiao updated https://github.com/llvm/llvm-project/pull/136556
>From 43e266b5a8f51ecd79df3156b20b48762699afd4 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Mon, 21 Apr 2025 04:18:56 -0400
Subject: [PATCH] [RISCV] Add smcntrpmf extension
spec: https://github.com/riscvarchive/riscv-smcntrpmf
---
.../Driver/print-supported-extensions-riscv.c | 1 +
.../test/Preprocessor/riscv-target-features.c | 9 +++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +++
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 10 ++++++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/test/MC/RISCV/machine-csr-names.s | 24 +++++++++++++++++++
llvm/test/MC/RISCV/rv32-machine-csr-names.s | 24 +++++++++++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 1 +
11 files changed, 81 insertions(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 39002d7b4780a..1f83910969221 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -123,6 +123,7 @@
// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
+// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 253e42419f453..03c291afe19bd 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -29,6 +29,7 @@
// CHECK-NOT: __riscv_shvstvecd {{.*$}}
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
+// CHECK-NOT: __riscv_smcntrpmf {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
@@ -1445,6 +1446,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32ismcntrpmf1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64ismcntrpmf1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
+// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}
+
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 137b537f00ea0..1ebe7b57abd7d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -128,6 +128,7 @@ on support follow.
``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Smaia`` Supported
``Smcdeleg`` Supported
+ ``Smcntrpmf`` Supported
``Smcsrind`` Supported
``Smdbltrp`` Supported
``Smepmp`` Supported
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f51fcf82077f4..87cab1dafc75b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -899,6 +899,9 @@ def FeatureStdExtSsaia
: RISCVExtension<1, 0,
"Advanced Interrupt Architecture Supervisor Level">;
+def FeatureStdExtSmcntrpmf
+ : RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;
+
def FeatureStdExtSmcsrind
: RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
def FeatureStdExtSscsrind
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 23388c7575e86..79ec8134733e8 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -482,6 +482,16 @@ def : SysReg<"sctrdepth", 0x15f>;
def : SysReg<"vsctrctl", 0x24e>;
def : SysReg<"mctrctl", 0x34e>;
+//===-----------------------------------------------
+// Cycle and Instret Privilege Mode Filtering (Smcntrpmf)
+//===-----------------------------------------------
+def : SysReg<"mcyclecfg", 0x321>;
+def : SysReg<"minstretcfg", 0x322>;
+let isRV32Only = 1 in {
+def : SysReg<"mcyclecfgh", 0x721>;
+def : SysReg<"minstretcfgh", 0x722>;
+} // isRV32Only
+
//===-----------------------------------------------
// Vendor CSRs
//===-----------------------------------------------
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 4bb3eb81f3dfb..b0dc65839559a 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -147,6 +147,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
+; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -301,6 +302,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
+; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -485,6 +487,7 @@
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
+; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -636,6 +639,7 @@
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
+; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index d377bda059d33..f7824ec10834c 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -129,6 +129,7 @@
; CHECK-NEXT: sifive7 - SiFive 7-Series processors.
; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
+; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 8edd6800a125f..16acd403eb9af 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -336,6 +336,9 @@
.attribute arch, "rv32i_smcdeleg1p0"
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
+.attribute arch, "rv32i_smcntrpmf1p0"
+# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"
+
.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 0a76636f060e6..016c14d6f840b 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -2733,3 +2733,27 @@ csrrs t2, 0x742, zero
csrrs t1, mnstatus, zero
# uimm12
csrrs t2, 0x744, zero
+
+# mcyclecfg
+# name
+# CHECK-INST: csrrs t1, mcyclecfg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x32]
+# CHECK-INST-ALIAS: csrr t1, mcyclecfg
+csrrs t1, mcyclecfg, zero
+# uimm12
+# CHECK-INST: csrrs t2, mcyclecfg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x32]
+# CHECK-INST-ALIAS: csrr t2, mcyclecfg
+csrrs t2, 0x321, zero
+
+# minstretcfg
+# name
+# CHECK-INST: csrrs t1, minstretcfg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x32]
+# CHECK-INST-ALIAS: csrr t1, minstretcfg
+csrrs t1, minstretcfg, zero
+# uimm12
+# CHECK-INST: csrrs t2, minstretcfg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x32]
+# CHECK-INST-ALIAS: csrr t2, minstretcfg
+csrrs t2, 0x322, zero
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 9e929b7eddeed..9fd19c36d5b93 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -1163,3 +1163,27 @@ csrrs t2, 0x319, zero
csrrs t1, miph, zero
# uimm12
csrrs t2, 0x354, zero
+
+# mcyclecfgh
+# name
+# CHECK-INST: csrrs t1, mcyclecfgh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x72]
+# CHECK-INST-ALIAS: csrr t1, mcyclecfgh
+csrrs t1, mcyclecfgh, zero
+# uimm12
+# CHECK-INST: csrrs t2, mcyclecfgh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x72]
+# CHECK-INST-ALIAS: csrr t2, mcyclecfgh
+csrrs t2, 0x721, zero
+
+# minstretcfgh
+# name
+# CHECK-INST: csrrs t1, minstretcfgh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x72]
+# CHECK-INST-ALIAS: csrr t1, minstretcfgh
+csrrs t1, minstretcfgh, zero
+# uimm12
+# CHECK-INST: csrrs t2, minstretcfgh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x72]
+# CHECK-INST-ALIAS: csrr t2, minstretcfgh
+csrrs t2, 0x722, zero
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 6e190ad3e7969..43896fede57d8 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1086,6 +1086,7 @@ R"(All available -march extensions for RISC-V
shvstvecd 1.0
smaia 1.0
smcdeleg 1.0
+ smcntrpmf 1.0
smcsrind 1.0
smdbltrp 1.0
smepmp 1.0
More information about the llvm-commits
mailing list