[llvm] [RISCV][NFC] Convert some predicates to TIIPredicate (PR #129658)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,143 @@
+//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instruction predicates.
+//
+//===----------------------------------------------------------------------===//
+
+// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
+def isSEXT_W
+    : TIIPredicate<"isSEXT_W",
+                   MCReturnStatement<CheckAll<[
+                     CheckOpcode<[ADDIW]>,
+                     CheckIsRegOperand<1>,
+                     CheckIsImmOperand<2>,
+                     CheckImmOperand<2, 0>
+                   ]>>>;
+
+// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
+def isZEXT_W
+    : TIIPredicate<"isZEXT_W",
+                   MCReturnStatement<CheckAll<[
+                     CheckOpcode<[ADD_UW]>,
+                     CheckIsRegOperand<1>,
+                     CheckIsRegOperand<2>,
+                     CheckRegOperand<2, X0>
+                   ]>>>;
+
+// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
+def isZEXT_B
+    : TIIPredicate<"isZEXT_B",
+                   MCReturnStatement<CheckAll<[
+                     CheckOpcode<[ANDI]>,
+                     CheckIsRegOperand<1>,
+                     CheckIsImmOperand<2>,
+                     CheckImmOperand<2, 255>
+                   ]>>>;
+
+// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
+def isSelectPseudo
+    : TIIPredicate<"isSelectPseudo",
+                   MCOpcodeSwitchStatement<
+                     [MCOpcodeSwitchCase<
+                        [Select_GPR_Using_CC_GPR,
+                         Select_GPR_Using_CC_Imm,
+                         Select_FPR16_Using_CC_GPR,
+                         Select_FPR16INX_Using_CC_GPR,
+                         Select_FPR32_Using_CC_GPR,
+                         Select_FPR32INX_Using_CC_GPR,
+                         Select_FPR64_Using_CC_GPR,
+                         Select_FPR64INX_Using_CC_GPR,
+                         Select_FPR64IN32X_Using_CC_GPR
+                        ],
+                        MCReturnStatement<TruePred>>],
+                      MCReturnStatement<FalsePred>>>;
+
+// Returns true if this is a vector configuration instruction.
+def isVectorConfigInstr
+    : TIIPredicate<"isVectorConfigInstr",
+                   MCReturnStatement<
+                     CheckOpcode<[
+                       PseudoVSETVLI,
+                       PseudoVSETVLIX0,
+                       PseudoVSETIVLI
+                     ]>>>;
+
+// Return true if this is 'vsetvli x0, x0, vtype' which preserves
+// VL and only sets VTYPE.
+def isVLPreservingConfig
+    : TIIPredicate<"isVLPreservingConfig",
+                   MCReturnStatement<
+                     CheckAll<[
+                       CheckOpcode<[PseudoVSETVLIX0]>,
+                       CheckRegOperand<0, X0>
+                     ]>>>;
+
+def isFloatScalarMoveOrScalarSplatInstr
+    : TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr",
+                   MCReturnStatement<
+                     CheckOpcode<!listflatten([
+                      !select<Instruction>(".*PseudoVFMV_S_F.*"),
----------------
topperc wrote:

> I just remove the beginning wildcards.

But shouldn't we use `^` so the regex engine will only try the match at the beginning for efficiency?

https://github.com/llvm/llvm-project/pull/129658