[llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)

[Princeton Ferro via llvm-commits]

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@@ -83,6 +83,8 @@ class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
   }
   unsigned getMinVectorRegisterBitWidth() const { return 32; }
 
+  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
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Prince781 wrote:

This line only disables expansion in the IR-level `ExpandReductions` pass, letting SelectionDAG handle it instead. There are different behaviors between the IR-level pass, DAGTypeLegalizer, and the implementation in NVPTX being considered:

- ExpandReductions uses shufflevectors to split the vector operand into two smaller vectors, partially reduce them, and so on.
- SelectionDAG achieves the same thing without using shufflevectors.
- This implementation groups nearby elements bottom-up. I think this is better for data dependences.

https://github.com/llvm/llvm-project/pull/136253