[llvm] [AArch64] Merge scaled and unscaled narrow zero stores (PR #136705)

[Guy David via llvm-commits]

================
@@ -892,11 +892,10 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
     OffsetImm = IOffsetInBytes;
 
   int NewOpcode = getMatchingWideOpcode(Opc);
-  bool FinalIsScaled = !TII->hasUnscaledLdStOffset(NewOpcode);
-
-  // Adjust final offset if the result opcode is a scaled store.
-  if (FinalIsScaled) {
-    int NewOffsetStride = FinalIsScaled ? TII->getMemScale(NewOpcode) : 1;
----------------
guy-david wrote:

Both are unrelated, but also don't introduce any changes in functionality.

https://github.com/llvm/llvm-project/pull/136705