[llvm] [AMDGPU] Support alloca in AS0 (PR #136584)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> > This is the wrong place to handle this. AMDGPUCodeGenPrepare cannot be used for lowering.
> 
> Then I wonder what `AMDGPUCodeGenPrepareImpl::visitAddrSpaceCastInst` is?

It's not lowering, it's hacking in a poor substitute for a nonnull flag on the instruction. It's not required. 

> 
> Also, the NVPTX handling you mentioned in another PR is also a IR pass. I think to lower it in the middle end instead of instruction selection can take advantage of existing middle end optimization, though AMDGPUCodeGenPrepare seems to be a little bit too late.

I never said what NVPTX does is good. If you implement getAssumedAddrSpace, you'll get the casting pattern which will be cleaned up in InferAddressSpaces at an earlier point. The backend just needs direct handling of the fallback case 

https://github.com/llvm/llvm-project/pull/136584