[llvm] [AArch64][SVE] Generate asrd instruction for positive pow-2 divisors … (PR #137151)

[Paul Walker via llvm-commits]

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@@ -18421,6 +18421,12 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
 
   EVT VT = N->getValueType(0);
 
+  // If SVE is available, we can generate
+  //  sdiv(x,y) -> ptrue + asrd          , where 'y' is positive pow-2 divisor.
+  //  sdiv(x,y) -> ptrue + asrd + subr   , where 'y' is negative pow-2 divisor.
+  if (Subtarget->hasSVE() && N->getValueType(0).isVector())
+    return SDValue(N, 0);
+
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paulwalker-arm wrote:

With the previous restriction removed I think you can just change the current bailout by replacing `useSVEForFixedLengthVectors()` with `isSVEorStreamingSVEAvailable()`? or perhaps change the whole line to `if (VT.isVector() && Subtarget->isSVEorStreamingSVEAvailable ())`?

https://github.com/llvm/llvm-project/pull/137151