[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Sander de Smalen via llvm-commits]

================
@@ -1830,6 +1830,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
   }
 
+  // Handle partial reduction operations
+  if (EnablePartialReduceNodes) {
+    if (Subtarget->isSVEorStreamingSVEAvailable()) {
+      // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
+      // Other pairs will default to 'Expand'.
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
+    }
+  }
----------------
sdesmalen-arm wrote:

nit:
```suggestion
  if (EnablePartialReduceNodes &&
      Subtarget->isSVEorStreamingSVEAvailable()) {
    // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
    // Other pairs will default to 'Expand'.
    setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
    setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
  }
```

https://github.com/llvm/llvm-project/pull/130933