[llvm] [AMDGPU] add s_bitset[10]_b32 optimization for shl+[or, andn2] pattern (PR #134155)

[via llvm-commits]

BaoshanPang wrote:

> > With the knowledage what I have so far, doing it in SiShrink pass is the easiest way.
> 
> This is more difficult than selecting this as a tablegen pattern
> 
> > to do it in fd file, we need to use different method for global-isel and non-global-isel.
> 
> This is not true
> 
> > in selection stage, the instructions are more generic and complex than what can be seen at post-select phase
> 
> The opposite is true. One generic operation becomes many more complicated selected operations

Ok, I guess I need to get better understanding of the system. For now, I will try to find some workable issues to fix. Please feel free to assign https://github.com/llvm/llvm-project/issues/130245 to others.

https://github.com/llvm/llvm-project/pull/134155