The Week Of Monday 18 September 2023 Archives by thread
Starting: Mon Sep 18 00:00:44 PDT 2023
Ending: Sun Sep 24 23:59:11 PDT 2023
Messages: 4896
- [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)
Ting Wang via llvm-commits
- [PATCH] D150684: [LoopReroll] Remove unused LoopReroll pass
dewen via Phabricator via llvm-commits
- [llvm] 87143ff - [VectorCombine] Fix a spot in commit 068357d9b09cd635b1c2f126d119ce9afecb28f7
Ben Shi via llvm-commits
- [llvm] Add myself to CODEOWNERS (PR #66363)
Nikita Popov via llvm-commits
- [llvm] [CodeGen] Renumber slot indexes before register allocation (PR #66334)
Carl Ritson via llvm-commits
- [PATCH] D157802: [JITLink][EHFrameSupport] Accept multiple relocations
Job Noorman via Phabricator via llvm-commits
- [llvm] d861b31 - [RISCV][NFC] precommit for D159399
Piyou Chen via llvm-commits
- [PATCH] D159400: [RISCV][NFC] precommit for D159399
Piyou Chen via Phabricator via llvm-commits
- [PATCH] D157803: [JITLink][RISCV] Implement eh_frame handling
Job Noorman via Phabricator via llvm-commits
- [PATCH] D159399: [RISCV] Only emit .option when extension is supported
Piyou Chen via Phabricator via llvm-commits
- [llvm] b83a1ed - [RISCV] Only emit .option when extension is supported
Piyou Chen via llvm-commits
- [llvm] Support target names with dots in more utilities (PR #65812)
James Henderson via llvm-commits
- [lld] Support target names with dots in more utilities (PR #65812)
James Henderson via llvm-commits
- [llvm] [SimplifyCFG] Delete the unnecessary range check for small mask operation (PR #65835)
via llvm-commits
- [PATCH] D159524: [BOLT] Speedup symbol table sort
Job Noorman via Phabricator via llvm-commits
- [llvm] [AMDGPU] Fix non-determinism in DenseSet (PR #66617)
David Stuttard via llvm-commits
- [llvm] [AMDGPU][MC][GFX11] Always output wait_vdst and wait_exp (PR #66610)
David Stuttard via llvm-commits
- [llvm] [CodeLayout] Fix X1_Y_X2 and Y_X2_X1 testing for jumps from Y (PR #66592)
via llvm-commits
- [llvm] [MemCpyOpt] fix miscompile for non-dominated use of src alloca for stack-move optimization (PR #66618)
Kohei Asano via llvm-commits
- [PATCH] D154205: [MachineLICM] Handle subloops
JinGu Kang via Phabricator via llvm-commits
- [llvm] [libc] Add monadic functions to cpp::expected (PR #66523)
Guillaume Chatelet via llvm-commits
- [PATCH] D158059: [AMDGPU/wmma] - Disable 3-address syntax for f16
Jessica Del via Phabricator via llvm-commits
- [PATCH] D124406: [X86] Use indirect addressing for high 2GB of x32 address space
Harald van Dijk via Phabricator via llvm-commits
- [PATCH] D159513: [Bolt] fix a relocation bug for R_AARCH64_CALL26
Sinan Lin via Phabricator via llvm-commits
- [PATCH] D157615: [ExtendLifetimes][1/4] Add "disable-post-ra" function attribute to disable the post-regalloc scheduler
Stephen Tozer via Phabricator via llvm-commits
- [llvm] [SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (PR #66601)
Simon Pilgrim via llvm-commits
- [PATCH] D158623: [RISCV] Reorder the stack frame objects.
lcvon via Phabricator via llvm-commits
- [llvm] [VP] Add missing functional_intrinsic properties and add static_assert. NFC (PR #66199)
Luke Lau via llvm-commits
- [llvm] [Sema] add cast from IncompleteArrayType to ConstantArrayType in TryReferenceListInitialization (PR #65918)
Mariya Podchishchaeva via llvm-commits
- [compiler-rt] [Sema] add cast from IncompleteArrayType to ConstantArrayType in TryReferenceListInitialization (PR #65918)
Mariya Podchishchaeva via llvm-commits
- [llvm] [InstCombine] optimize exp(exp(x)) / exp(x) with fast-math (PR #66177)
Zain Jaffal via llvm-commits
- [llvm] ce031fc - [AMDGPU] Fix non-deterministic iteration order in SIFixSGPRCopies (#66617)
via llvm-commits
- [llvm] dd55ece - [ValueTracking] Remove unused Depth parameter (NFC)
Nikita Popov via llvm-commits
- [llvm] [AArch64] Remove copy instruction between uaddlv with v4i16/v8i16 and dup (PR #66508)
David Green via llvm-commits
- [llvm] add a unit test for the segfault in rust after https://reviews.llvm.org/D159485 (PR #66491)
Krasimir Georgiev via llvm-commits
- [llvm] [InstCombine] Create a class to lazily track computed known bits (PR #66611)
Nikita Popov via llvm-commits
- [PATCH] D154793: [DWARFLinkerParallel] Add support of accelerator tables to DWARFLinkerParallel.
Alexey Lapshin via Phabricator via llvm-commits
- [llvm] [RISCV] Combine vslidedown_vl with known VL to a smaller LMUL (PR #66267)
Luke Lau via llvm-commits
- [llvm] [llvm][documentation] Fix coroutines documentation (PR #66420)
Chuanqi Xu via llvm-commits
- [llvm] [clang] Enable --print-supported-extensions for all targets (PR #66586)
David Spickett via llvm-commits
- [llvm] 7a472a0 - [llvm][documentation] Fix coroutines documentation (#66420)
via llvm-commits
- [llvm] [NewGVN] Set parent to the temporal instructions that are generated during phi-of-ops optimization (PR #66314)
Nikita Popov via llvm-commits
- [llvm] Test for future commit in NewGVN (PR #66313)
Nikita Popov via llvm-commits
- [PATCH] D152828: [MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode
Momchil Velikov via Phabricator via llvm-commits
- [llvm] [ConstraintElimination] Extend unsigned-to-signed fact transfer (PR #66173)
Nikita Popov via llvm-commits
- [llvm] [Inliner] Improve attribute propagation to callsites when inlining. (PR #66036)
Nikita Popov via llvm-commits
- [llvm] [SPIRV] Implement support for SPV_KHR_expect_assume (PR #66217)
Paulo Matos via llvm-commits
- [llvm] [RISCV] Combine vslidedown_vl with known VL and offset to a smaller LMUL (PR #66267)
Luke Lau via llvm-commits
- [PATCH] D119412: github: Automatically create backport requests for bugs referenced in commit messages
Konrad Wilhelm Kleine via Phabricator via llvm-commits
- [llvm] [AMDGPU][GFX11] Do not rewrite V_FMA/FMAC_* to V_FMAAK_F16_t16 on operand legalization. (PR #66202)
Ivan Kosarev via llvm-commits
- [llvm] [RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (PR #66087)
Luke Lau via llvm-commits
- [PATCH] D158861: [llvm] Move CallInst::CreateMalloc to IRBuilderBase::CreateMalloc
Konrad Wilhelm Kleine via Phabricator via llvm-commits
- [llvm] [SDag] Fold saddo[_carry] with bitwise-not argument to ssubo[_carry] (PR #66571)
Nikita Popov via llvm-commits
- [PATCH] D157977: [InstCombine] OptimizePointerDifference when a gep has phi ptr
Biplob Mishra via Phabricator via llvm-commits
- [llvm] [mlir][bufferization] Add OwnershipBasedBufferDeallocation pass option to forbid clones (PR #66626)
Martin Erhart via llvm-commits
- [llvm] update_mir_test_checks.py: match undef vreg subreg definitions (PR #66627)
Jay Foad via llvm-commits
- [compiler-rt] [sanitizers] Do not define __has_feature in sanitizer/common_interface_defs.h (PR #66628)
Jonathan Wakely via llvm-commits
- [PATCH] D158574: [AArch64][ELF] Support PAUTH ABI marking
Peter Smith via Phabricator via llvm-commits
- [PATCH] D159073: [PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.
Qiu Chaofan via Phabricator via llvm-commits
- [llvm] [SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore. (PR #66567)
Simon Pilgrim via llvm-commits
- [llvm] [SSP] Accessing __stack_chk_guard when using LTO (PR #66535)
Simon Pilgrim via llvm-commits
- [PATCH] D159471: [DWARFVerifier] Allow ObjectiveC names in dwarf_debug tables
Felipe de Azevedo Piovezan via Phabricator via llvm-commits
- [PATCH] D159468: [AsmPrinter][DwarfDebug] Skip vars with fragments in different location kinds
Felipe de Azevedo Piovezan via Phabricator via llvm-commits
- [PATCH] D157549: [LV] Add debug output to print interleaved groups
Ayal Zaks via Phabricator via llvm-commits
- [llvm] 102838d - update_mir_test_checks.py: match undef vreg subreg definitions (#66627)
via llvm-commits
- [PATCH] D158843: [ConstraintElim] Move just before loop simplification pipeline.
Florian Hahn via Phabricator via llvm-commits
- [PATCH] D152730: [ConstraintElim] Add A < B if A is an increasing phi for A != B.
Florian Hahn via Phabricator via llvm-commits
- [PATCH] D159200: [VPlan] Fold (MUL A, 1) -> A as VPlan2VPlan transform.
Florian Hahn via Phabricator via llvm-commits
- [llvm] [RISCV] Match prefetch address with offset (PR #66072)
Wang Pengcheng via llvm-commits
- [llvm] [LLVM] Add new attribute `optdebug` to optimize for debugging (PR #66632)
Stephen Tozer via llvm-commits
- [llvm] caaf61e - [SDag] Fold saddo[_carry] with bitwise-not argument to ssubo[_carry] (#66571)
via llvm-commits
- [llvm] [AMDGPU][MISCHED] GCNBalancedSchedStrategy. (PR #66634)
via llvm-commits
- [PATCH] D157694: [RISCV][MC]Add support for Binary MCExpr
Yvan Roux via Phabricator via llvm-commits
- [llvm] baf031a - [MemCpyOpt] fix miscompile for non-dominated use of src alloca for stack-move optimization (#66618)
via llvm-commits
- [llvm] [Documentation] Replace recommonmark by myst-parser (PR #65664)
via llvm-commits
- [llvm] [mlir][bufferization] Move memref specific implementation of AllocationOpInterface to memref dialect directory (PR #66637)
Martin Erhart via llvm-commits
- [llvm] [LV] Increase max VF if vectorized function variants exist (PR #66639)
via llvm-commits
- [llvm] [RISCV] Fix inline asm error for block address (PR #66640)
Wang Pengcheng via llvm-commits
- [compiler-rt] b3ca0f3 - [scudo] Use MemMap in Vector
Fabio D'Urso via llvm-commits
- [llvm] 162bafc - [SVE] Fix crash when costing getelementptr with scalable target type.
Paul Walker via llvm-commits
- [llvm] 4491f0b - [IR] Remove unnecessary bitcast from CreateMalloc()
Nikita Popov via llvm-commits
- [PATCH] D157458: [X86] Run X86FastPreTileConfigPass only with FastISel.
Quentin Colombet via Phabricator via llvm-commits
- [llvm] [AArch64] Fix pairing different types of registers when computing CSRs. (PR #66642)
Zhaoxuan Jiang via llvm-commits
- [llvm] [LiveRegUnits] Enhanced the register liveness check (PR #66061)
via llvm-commits
- [llvm] [EarlyCSE] Compare GEP instructions based on offset (PR #65875)
Nikita Popov via llvm-commits
- [llvm] [Github] Improve formating of PR diffs in bot notifications (PR #66118)
Jay Foad via llvm-commits
- [llvm] [mlir][bufferization] Empty tensor elimination for materialize_in_destination (PR #65468)
Nicolas Vasilache via llvm-commits
- [llvm] [Interpreter] Add initialization of array members (PR #66172)
via llvm-commits
- [llvm] [InstSimplify] Fold icmp of `X and/or C1` and `X and/or C2` into constant (PR #65905)
Yingwei Zheng via llvm-commits
- [llvm] be2723d - [InstSimplify] Fold icmp of `X and/or C1` and `X and/or C2` into constant (#65905)
via llvm-commits
- [PATCH] D159202: [VPlan] Simplify redundant trunc (zext A) pairs to A.
Ayal Zaks via Phabricator via llvm-commits
- [llvm] [SelectionDAG] Flags are dropped when creating FMUL (PR #66646)
Sirish Pande via llvm-commits
- [llvm] [TwoAddressInstruction] Update LiveIntervals after INSERT_SUBREG with undef read (PR #66211)
via llvm-commits
- [llvm] [LAA] Analyze pointers forked by a phi (PR #65834)
via llvm-commits
- [compiler-rt] [scudo] Enable "Delayed release to OS" feature for Android (PR #65942)
via llvm-commits
- [llvm] d8d0588 - [TwoAddressInstruction] Update LiveIntervals after INSERT_SUBREG with undef read (#66211)
via llvm-commits
- [llvm] [InstCombine] Simplify the pattern `a ne/eq (zext (a ne/eq c))` (PR #65852)
Yingwei Zheng via llvm-commits
- [PATCH] D152840: [ELF] A new code layout algorithm for function reordering [3a/3]
Sergey Pupyrev via Phabricator via llvm-commits
- [llvm] [VectorCombine][RISCV] Convert VPIntrinsics with splat operands to splats (PR #65706)
Michael Maitland via llvm-commits
- [llvm] [RISCV] Fix bugs about getting register list of Zcmp push/pop. (PR #66073)
Yeting Kuo via llvm-commits
- [llvm] [libc++] Prevent calling the projection more than three times (PR #66315)
Louis Dionne via llvm-commits
- [compiler-rt] [libc++] Prevent calling the projection more than three times (PR #66315)
Louis Dionne via llvm-commits
- [llvm] c7aacbb - [ArgPromotion] Update allocsize indices after promotion
Nikita Popov via llvm-commits
- [llvm] AMDGPU: Fix handling of -0 in round lowering (PR #65761)
Joseph Huber via llvm-commits
- [llvm] 3ce8eda - [Github] Add a new line before the line separator to avoid paragraphs being treated as titles
Corentin Jabot via llvm-commits
- [llvm] [IGNORE] Test PR to troubleshoot potential CI issue (PR #66650)
Louis Dionne via llvm-commits
- [llvm] [Support] Remove redundant forwarding functions read/write (NFC) (PR #66051)
Louis Dionne via llvm-commits
- [PATCH] D158743: [Verifier] Sanity check alloca size against DILocalVariable fragment size
Krasimir Georgiev via Phabricator via llvm-commits
- [llvm] dc11814 - [InstCombine] Add pre-commit tests for PR65073. NFC.
Yingwei Zheng via llvm-commits
- [llvm] Introduce paged vector (PR #66430)
Jakub Kuderski via llvm-commits
- [PATCH] D156099: [AMDGPU] Add True16 register classes.
Ivan Kosarev via Phabricator via llvm-commits
- [llvm] b2ffc86 - [DAG] getNode() - begin generalizing the (zext (trunc (assertzext x))) -> (assertzext x) fold.
Simon Pilgrim via llvm-commits
- [llvm] [llvm-libgcc][CMake] Refactor llvm-libgcc (PR #65455)
Louis Dionne via llvm-commits
- [lld] [LLD][AARCH64] lld incorrectly handles .eh_frame when it has a non-zero offset within its output section. (PR #65966)
via llvm-commits
- [PATCH] D159357: [AArch64] Move PAuth codegen down the machine pipeline
Anatoly Trosinenko via Phabricator via llvm-commits
- [PATCH] D155688: [PATCH] [llvm] [InstCombine] Reassociate loop invariant GEP index calculations.
Dmitriy Smirnov via Phabricator via llvm-commits
- [PATCH] D156101: [AMDGPU] Introduce real and keep fake True16 instructions.
Ivan Kosarev via Phabricator via llvm-commits
- [llvm] [MachineBasicBlock] Fix use after free in SplitCriticalEdge (PR #66188)
via llvm-commits
- [llvm] [AArch64] Remove the Z#_HI register definitions (PR #66353)
via llvm-commits
- [llvm] 5aa8e43 - [VP] Add missing functional_intrinsic properties and add static_assert. NFC (#66199)
via llvm-commits
- [llvm] Bfi precision (PR #66285)
via llvm-commits
- [llvm] 38c59b9 - Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"
Nikita Popov via llvm-commits
- [llvm] [Clang] Allow mixed scalar type constraints for inline asm (PR #65465)
Dávid Ferenc Szabó via llvm-commits
- [llvm] Fix mechanism propagating mangled names for TLI function mappings (PR #66656)
via llvm-commits
- [llvm] [AArch64] Fix incorrect big-endian spill in foldMemoryOperandImpl (PR #65601)
via llvm-commits
- [llvm] [mlir][bufferization] BufferDeallocation: support unstructured control flow loops (PR #66657)
Martin Erhart via llvm-commits
- [llvm] [LoopPredication] Fix division by zero in case of zero branch weights (PR #66506)
Danila Malyutin via llvm-commits
- [llvm] 13a74d6 - [RISCV] Fix crash when legalizing mgather/scatter on rv32
Philip Reames via llvm-commits
- [llvm] [RISCV] Prefer vrgatherei16 for shuffles (PR #66291)
Philip Reames via llvm-commits
- [llvm] [RISCV] Optimize gather/scatter to unit-stride memop + shuffle (PR #66279)
Philip Reames via llvm-commits
- [llvm] [CodeGen] Allow mixed scalar type constraints for inline asm (PR #65465)
Dávid Ferenc Szabó via llvm-commits
- [llvm] specify NaN behavior more precisely (PR #66579)
Joshua Cranmer via llvm-commits
- [llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)
Luke Lau via llvm-commits
- [llvm] [mlir][sparse] refine sparse fusion with empty tensors materialization (PR #66563)
Aart Bik via llvm-commits
- [llvm] f71a9e8 - [SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)
via llvm-commits
- [llvm] [Attributor] New attribute to identify what byte ranges are alive for an allocation (PR #66148)
Johannes Doerfert via llvm-commits
- [compiler-rt] [asan][Windows] Add additional wcs* interceptors (PR #66128)
nicole mazzuca via llvm-commits
- [llvm] 17a12a2 - [RISCV] Add test case to show bad codegen for unaligned i64 store of a large constant.
Craig Topper via llvm-commits
- [llvm] 8f04d81 - [SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore.
Craig Topper via llvm-commits
- [llvm] [WIP][AMDGPU] Adjust asan instrumented GlobalVaribale size to not include redzone (PR #66666)
via llvm-commits
- [llvm] be16b03 - [AArch64] Remove the Z#_HI register definitions (#66353)
via llvm-commits
- [llvm] [RISCV][NFC] Simplify the sp-offset reduction by spimm of CM.PUSH/POP. (PR #66667)
Yeting Kuo via llvm-commits
- [llvm] [InstSimplify] Simplify the select with integer comparison relationship (PR #66668)
via llvm-commits
- [llvm] bb7b872 - [RISCV] Merge some test checks rvv/fixed-vectors-masked-gather.ll [nfc]
Philip Reames via llvm-commits
- [PATCH] D146169: Non-debuginfo JITLink perf jitdump support
Vitaly Buka via Phabricator via llvm-commits
- [lld] [mlir][sparse] refine sparse fusion with empty tensors materialization (PR #66563)
Aart Bik via llvm-commits
- [compiler-rt] [mlir][sparse] refine sparse fusion with empty tensors materialization (PR #66563)
Aart Bik via llvm-commits
- [llvm] 0722800 - [RISCV] Match constant indices of non-index type when forming strided ops (#65777)
Philip Reames via llvm-commits
- [llvm] [RISCV] Match constant indices of non-index type when forming strided ops (PR #65777)
Philip Reames via llvm-commits
- [PATCH] D156087: [MLIR] Add stage to side effect
Jeff Niu via Phabricator via llvm-commits
- [llvm] cb9f66d - [Profile] Pass InstrProfSymtab instead of IndexedInstrProfReader when creating BinaryCoverageReader
Zequan Wu via llvm-commits
- [llvm] 83e6d2e - Revert "[ARM] Always lower direct calls as direct when the outliner is enabled (#66434)"
Jon Roelofs via llvm-commits
- [PATCH] D158600: [InferAlignment] Enable InferAlignment pass by default
Dhruv Chawla via Phabricator via llvm-commits
- [llvm] [ARM] Always lower direct calls as direct when the outliner is enabled (PR #66434)
Jon Roelofs via llvm-commits
- [PATCH] D158530: [InferAlignment] Create tests for InferAlignment pass
Dhruv Chawla via Phabricator via llvm-commits
- [llvm] [mlir][sparse] fix merge conflict in sddmm test (PR #66670)
Aart Bik via llvm-commits
- [PATCH] D158529: [InferAlignment] Implement InferAlignmentPass
Dhruv Chawla via Phabricator via llvm-commits
- [PATCH] D158527: [InstCombine] Add a cl::opt to control calls to getOrEnforceKnownAlignment in LoadInst and StoreInst
Dhruv Chawla via Phabricator via llvm-commits
- [llvm] [VectorCombine] Enable transform 'scalarizeLoadExtract' for scalable vector types (PR #65443)
via llvm-commits
- [PATCH] D159322: LoopVectorize: Set branch_weight for conditional branches
Wenlei He via Phabricator via llvm-commits
- [llvm] [RISCV] Combine vslideup_vl with known VL to a smaller LMUL (PR #66671)
Luke Lau via llvm-commits
- [llvm] 2a38d83 - [InstSimplify] Add pre-commits for PR#66606. NFC.
Yingwei Zheng via llvm-commits
- [llvm] [llvm][dwarf][rfc][donotcommit] Enable print of ranges addresses from .debug_info.dwo (PR #65516)
Alexander Yermolovich via llvm-commits
- [llvm] [AArch64][SVE2] Do not emit RSHRNB for large shifts (PR #66672)
Matthew Devereau via llvm-commits
- [llvm] 135e521 - [NewGVN] Set parent to the temporal instructions that are generated during phi-of-ops optimization (#66314)
via llvm-commits
- [llvm] [TargetMachine] Remove DefaultOptions (PR #66673)
Arthur Eubanks via llvm-commits
- [PATCH] D159521: [BOLT][runtime] Test for outline-atomics support
Vladislav Khmelevsky via Phabricator via llvm-commits
- [PATCH] D159520: [BOLT][AArch64] Fix instrumentation deadloop
Vladislav Khmelevsky via Phabricator via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
Yingwei Zheng via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
Nikita Popov via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
Yingwei Zheng via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
Yingwei Zheng via llvm-commits
- [llvm] [InstSimplify] Fold `and A, (zext (icmp eq A, 0))` into 0 (PR #66676)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Add a combine to form masked.store from unit strided store (PR #66677)
Philip Reames via llvm-commits
- [llvm] d10ee89 - [InstCombine] Add `sext` version of pre-commit tests for PR65852. NFC.
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Narrow indices of fixed vector gather/scatter nodes (PR #66405)
Philip Reames via llvm-commits
- [llvm] [llvm-profgen] Ignore inline frames with an emtpy function name (PR #66678)
Hongtao Yu via llvm-commits
- [llvm] 8677aaa - [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
Craig Topper via llvm-commits
- [llvm] [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64. (PR #65663)
Craig Topper via llvm-commits
- [llvm] [InstCombine] Optimize 'xor-and/or-select' sequence to 'or' for bool (PR #66394)
Qi Hu via llvm-commits
- [llvm] [cmake] Option to create Ninja job pools depending on available resources (PR #65274)
via llvm-commits
- [llvm] cbd0428 - [gn] port 8677aaa1a32a (RISCV pre-legalizer combiners)
Nico Weber via llvm-commits
- [llvm] [InlineCost] Enable the cost benefit analysis for Sample PGO (PR #66457)
Kazu Hirata via llvm-commits
- [PATCH] D159526: [CodeLayout] Refactor some std::vector and nested std::pair uses. NFC
David Blaikie via Phabricator via llvm-commits
- [llvm] 1609a87 - [Profile] Pass InstrProfSymtab by reference.
Zequan Wu via llvm-commits
- [llvm] LoopRotationUtils: Fix underflow for zero-branch weights (PR #66681)
Matthias Braun via llvm-commits
- [compiler-rt] DO_NOT_MERGE (PR #66682)
Vitaly Buka via llvm-commits
- [PATCH] D159525: [BOLT][NFC] Refactor RI::discoverFileObjects()
Maksim Panchenko via Phabricator via llvm-commits
- [llvm] c2e248c - [InstCombine] Fix typo in the test `icmp-range.ll`. NFC.
Yingwei Zheng via llvm-commits
- [PATCH] D158291: [PoC][WIP] Add an AArch64 specific pass for loop idiom recognition
Craig Topper via Phabricator via llvm-commits
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Shilei Tian via llvm-commits
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Yingwei Zheng via llvm-commits
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Hau Hsu via llvm-commits
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Congcong Cai via llvm-commits
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Kohei Asano via Phabricator via llvm-commits
- [llvm] 45bb45f - [llvm] Move CallInst::CreateMalloc to IRBuilderBase::CreateMalloc
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Yeting Kuo via Phabricator via llvm-commits
- [llvm] da57ced - [examples] Remove unused variable 'BB' in BrainF.cpp (NFC)
Jie Fu via llvm-commits
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Qiu Chaofan via Phabricator via llvm-commits
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Freddy Ye via llvm-commits
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Michal Paszkowski via llvm-commits
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Haojian Wu via llvm-commits
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Nikita Popov via llvm-commits
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Liqiang Tao via llvm-commits
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Simon Pilgrim via llvm-commits
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Simon Pilgrim via llvm-commits
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Luke Lau via Phabricator via llvm-commits
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- [llvm] [AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG (PR #66914)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
Ramkumar Ramachandra via llvm-commits
- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
Ramkumar Ramachandra via llvm-commits
- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
Ramkumar Ramachandra via llvm-commits
- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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- [llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)
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Vitaly Buka via llvm-commits
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Lang Hames via llvm-commits
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Lang Hames via llvm-commits
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Joseph Huber via llvm-commits
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Philip Reames via llvm-commits
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William Junda Huang via llvm-commits
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Michael Maitland via llvm-commits
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Felipe de Azevedo Piovezan via llvm-commits
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Jun Wang via llvm-commits
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Arthur Eubanks via llvm-commits
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Christopher Ferris via llvm-commits
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Lei Huang via llvm-commits
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Nitin John Raj via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
- [llvm] [TableGen][RISCV][GlobalISel] Select G_ICMP, G_SELECT, G_PTR_ADD (PR #67185)
Craig Topper via llvm-commits
- [llvm] [TableGen][RISCV][GlobalISel] Select G_ICMP, G_SELECT, G_PTR_ADD (PR #67185)
Craig Topper via llvm-commits
- [llvm] [TableGen][RISCV][GlobalISel] Select G_ICMP, G_SELECT, G_PTR_ADD (PR #67185)
Craig Topper via llvm-commits
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Min-Yih Hsu via llvm-commits
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Min-Yih Hsu via llvm-commits
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Michael Maitland via llvm-commits
- [llvm] [TableGen][RISCV][GlobalISel] Select G_ICMP, G_SELECT, G_PTR_ADD (PR #67185)
Michael Maitland via llvm-commits
- [llvm] [TableGen][RISCV][GlobalISel] Select G_ICMP, G_SELECT, G_PTR_ADD (PR #67185)
Michael Maitland via llvm-commits
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Michael Maitland via llvm-commits
- [llvm] [MachineLICM] Relax overlay conservative PHI check (PR #67186)
Hendrik Greving via llvm-commits
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Peter Rong via Phabricator via llvm-commits
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Craig Topper via llvm-commits
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Lang Hames via llvm-commits
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