[llvm] [RISCV] Use software guarded branch for indirect jump table branch. (PR #66762)

[Philip Reames via llvm-commits]

preames wrote:

I think I'm missing something fundamental about the implementation status here.  The GPRJALR register class used by BRIND (the non-guarded form) doesn't seem to exclude X7.  Given that, how is it useful to define a guarded form which requires X7?

Has there been an assembly syntax defined for the SW guarded branch?  An alias or anything else?  I don't see one in the linked specification (despite defining an alias for landing pad).  Having disassembler support for guarded branches would normally be a first step...

https://github.com/llvm/llvm-project/pull/66762