[llvm] [AArch64][SVE2] Do not emit RSHRNB for large shifts (PR #66672)

[via llvm-commits]

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@@ -20241,6 +20241,10 @@ static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG,
     return SDValue();
   unsigned ShiftValue = SrlOp1->getZExtValue();
 
+  uint64_t EltSize = ResVT.getScalarSizeInBits();
+  if (ShiftValue > EltSize)
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paulwalker-arm wrote:

Sorry Matt this was my fault. My question arose from the typically behaviour of right shifts that are greater than the element bit length, whereby `i32 >> #32+N == i32 >> #32`.

Dave pointed out that in this case the element type in question is actually half sized because the combine is only expected to be called when a truncate is in play. That would imply `i32 >> 16+N == i32 >> 16`, which is clearly bogus.

https://github.com/llvm/llvm-project/pull/66672