[llvm] [X86] Add missed type extension when combining load for ptr32 (PR #67168)
Evgenii Kudriashov via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 12:49:53 PDT 2023
https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/67168
>From 488a1838bbae59d81634bdea060ef671902935f3 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Thu, 21 Sep 2023 10:03:09 -0700
Subject: [PATCH 1/2] [X86] Add missed type extension when combining load for
ptr32
Closes #66873
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll | 13 ++++++++++++
llvm/test/CodeGen/X86/mixed-ptr-sizes.ll | 20 +++++++++++++++++++
3 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 81aa998d33c639b..484f39aaff722b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -49796,9 +49796,9 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
if (PtrVT != Ld->getBasePtr().getSimpleValueType()) {
SDValue Cast =
DAG.getAddrSpaceCast(dl, PtrVT, Ld->getBasePtr(), AddrSpace, 0);
- return DAG.getLoad(RegVT, dl, Ld->getChain(), Cast, Ld->getPointerInfo(),
- Ld->getOriginalAlign(),
- Ld->getMemOperand()->getFlags());
+ return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,
+ Ld->getPointerInfo(), MemVT, Ld->getOriginalAlign(),
+ Ld->getMemOperand()->getFlags());
}
}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
index 0817211f50937ed..fe41f76bfb16515 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
@@ -341,3 +341,16 @@ entry:
store i32 %i, ptr addrspace(272) %s, align 8
ret void
}
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; ALL-LABEL: test_load_sptr32_zext_i64:
+; ALL: # %bb.0: # %entry
+; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax
+; ALL-NEXT: movl (%eax), %eax
+; ALL-NEXT: xorl %edx, %edx
+; ALL-NEXT: retl
+entry:
+ %0 = load i32, ptr addrspace(270) %i, align 4
+ %1 = zext i32 %0 to i64
+ ret i64 %1
+}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index e88a494908701d8..56223bbb28aeac9 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -256,3 +256,23 @@ entry:
store i32 %i, ptr addrspace(272) %s, align 8
ret void
}
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; CHECK-LABEL: test_load_sptr32_zext_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movslq %ecx, %rax
+; CHECK-NEXT: movl (%rax), %eax
+; CHECK-NEXT: retq
+;
+; CHECK-O0-LABEL: test_load_sptr32_zext_i64:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: movslq %ecx, %rax
+; CHECK-O0-NEXT: movl (%rax), %eax
+; CHECK-O0-NEXT: movl %eax, %eax
+; CHECK-O0-NEXT: # kill: def $rax killed $eax
+; CHECK-O0-NEXT: retq
+entry:
+ %0 = load i32, ptr addrspace(270) %i, align 4
+ %1 = zext i32 %0 to i64
+ ret i64 %1
+}
>From d95ac26d11dfda049056602e422bca1a96dfedb7 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Fri, 22 Sep 2023 12:22:31 -0700
Subject: [PATCH 2/2] amend! [X86] Add missed type extension when combining
load for ptr32
[X86] Add missed type extension and truncation during combine
Type extension and truncation is missed when combining loads and stores
for ptr32 and ptr64.
Closes #66873
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++---
llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll | 23 +++++++++++++++++++
llvm/test/CodeGen/X86/mixed-ptr-sizes.ll | 21 +++++++++++++++++
3 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 484f39aaff722b6..1b427398484ad9b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50300,9 +50300,10 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
if (PtrVT != St->getBasePtr().getSimpleValueType()) {
SDValue Cast =
DAG.getAddrSpaceCast(dl, PtrVT, St->getBasePtr(), AddrSpace, 0);
- return DAG.getStore(St->getChain(), dl, StoredVal, Cast,
- St->getPointerInfo(), St->getOriginalAlign(),
- St->getMemOperand()->getFlags(), St->getAAInfo());
+ return DAG.getTruncStore(
+ St->getChain(), dl, StoredVal, Cast, St->getPointerInfo(), StVT,
+ St->getOriginalAlign(), St->getMemOperand()->getFlags(),
+ St->getAAInfo());
}
}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
index fe41f76bfb16515..c997d314a50ae4c 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
@@ -354,3 +354,26 @@ entry:
%1 = zext i32 %0 to i64
ret i64 %1
}
+
+define void @test_store_sptr32_trunc_i1(ptr addrspace(270) %s, i32 %i) {
+; CHECK-LABEL: test_store_sptr32_trunc_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: andl $1, %ecx
+; CHECK-NEXT: movb %cl, (%eax)
+; CHECK-NEXT: retl
+;
+; CHECK-O0-LABEL: test_store_sptr32_trunc_i1:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-O0-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-O0-NEXT: andl $1, %ecx
+; CHECK-O0-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-O0-NEXT: movb %cl, (%eax)
+; CHECK-O0-NEXT: retl
+entry:
+ %0 = trunc i32 %i to i1
+ store i1 %0, ptr addrspace(270) %s
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index 56223bbb28aeac9..67539b07f5716c1 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -276,3 +276,24 @@ entry:
%1 = zext i32 %0 to i64
ret i64 %1
}
+
+define void @test_store_sptr32_trunc_i1(ptr addrspace(270) %s, i32 %i) {
+; CHECK-LABEL: test_store_sptr32_trunc_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movslq %ecx, %rax
+; CHECK-NEXT: andl $1, %edx
+; CHECK-NEXT: movb %dl, (%rax)
+; CHECK-NEXT: retq
+;
+; CHECK-O0-LABEL: test_store_sptr32_trunc_i1:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: movslq %ecx, %rax
+; CHECK-O0-NEXT: andl $1, %edx
+; CHECK-O0-NEXT: movb %dl, %cl
+; CHECK-O0-NEXT: movb %cl, (%rax)
+; CHECK-O0-NEXT: retq
+entry:
+ %0 = trunc i32 %i to i1
+ store i1 %0, ptr addrspace(270) %s
+ ret void
+}
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