[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Luke Lau via llvm-commits]

================
@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
----------------
lukel97 wrote:

I think I'm missing something here. Are you saying that we don't currently allow a m1 vmv.s.x to be turned into a m4 vmv.s.x?

If we construct this example below where the vadd.vi has m4 (%1:vrm4), and the vmv.s.x has m1 (%3:vr)

```
---
name: lmul_merge
body:        |
  bb.0:
    liveins: $v0, $x1, $x2
    %vl:gprnox0 = COPY $x1

    %0:vrm4 = COPY $v0
    %pt0:vrm4 = IMPLICIT_DEF
    %1:vrm4 = PseudoVADD_VI_M4 %pt0, %0, 1, %vl, 6, 0
    
    %2:gpr = COPY $x2
    %pt1:vr = IMPLICIT_DEF
    %3:vr = PseudoVMV_S_X_M1 %pt1, %2, %vl, 6
    PseudoRET
```

Running `llc -o - -run-pass=riscv-insert-vsetvli -mtriple=riscv64 -mattr=+v -verify-machineinstrs`, it looks like we do relax the LMUL for vmv.s.x:

```
body:             |
  bb.0:
    liveins: $v0, $x1, $x2
  
    %vl:gprnox0 = COPY $x1
    %1:vrm4 = COPY $v0
    %pt0:vrm4 = IMPLICIT_DEF
    dead $x0 = PseudoVSETVLI %vl, 218 /* e64, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
    %3:vrm4 = PseudoVADD_VI_M4 %pt0, %1, 1, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    %4:gpr = COPY $x2
    %pt1:vr = IMPLICIT_DEF
    %6:vr = PseudoVMV_S_X_M1 %pt1, %4, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
    PseudoRET
```

I see what you mean about the legality though: Does the register allocator here know not to allocate v1/v2/v3 etc for %6, given its vtype will be M4?

https://github.com/llvm/llvm-project/pull/66659