[llvm] cbd0428 - [gn] port 8677aaa1a32a (RISCV pre-legalizer combiners)
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 18 11:10:20 PDT 2023
Author: Nico Weber
Date: 2023-09-18T14:10:14-04:00
New Revision: cbd0428d8bb5c0686d8bfb960cbcd851d046fcb2
URL: https://github.com/llvm/llvm-project/commit/cbd0428d8bb5c0686d8bfb960cbcd851d046fcb2
DIFF: https://github.com/llvm/llvm-project/commit/cbd0428d8bb5c0686d8bfb960cbcd851d046fcb2.diff
LOG: [gn] port 8677aaa1a32a (RISCV pre-legalizer combiners)
Added:
Modified:
llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Removed:
################################################################################
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 7af558ca1d59d1f..863b760a9028f9d 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -26,12 +26,30 @@ tablegen("RISCVGenGlobalISel") {
td_file = "RISCVGISel.td"
}
+tablegen("RISCVGenO0PreLegalizeGICombiner") {
+ visibility = [ ":LLVMRISCVCodeGen" ]
+ args = [
+ "-gen-global-isel-combiner",
+ "-combiners=RISCVO0PreLegalizerCombiner",
+ ]
+ td_file = "RISCVGISel.td"
+}
+
tablegen("RISCVGenMCPseudoLowering") {
visibility = [ ":LLVMRISCVCodeGen" ]
args = [ "-gen-pseudo-lowering" ]
td_file = "RISCV.td"
}
+tablegen("RISCVGenPreLegalizeGICombiner") {
+ visibility = [ ":LLVMRISCVCodeGen" ]
+ args = [
+ "-gen-global-isel-combiner",
+ "-combiners=RISCVPreLegalizerCombiner",
+ ]
+ td_file = "RISCVGISel.td"
+}
+
tablegen("RISCVGenRegisterBank") {
visibility = [ ":LLVMRISCVCodeGen" ]
args = [ "-gen-register-bank" ]
@@ -43,7 +61,9 @@ static_library("LLVMRISCVCodeGen") {
":RISCVGenCompressInstEmitter",
":RISCVGenDAGISel",
":RISCVGenGlobalISel",
+ ":RISCVGenO0PreLegalizeGICombiner",
":RISCVGenMCPseudoLowering",
+ ":RISCVGenPreLegalizeGICombiner",
":RISCVGenRegisterBank",
# See https://reviews.llvm.org/D69130
@@ -67,6 +87,8 @@ static_library("LLVMRISCVCodeGen") {
"GISel/RISCVCallLowering.cpp",
"GISel/RISCVInstructionSelector.cpp",
"GISel/RISCVLegalizerInfo.cpp",
+ "GISel/RISCVO0PreLegalizerCombiner.cpp",
+ "GISel/RISCVPreLegalizerCombiner.cpp",
"GISel/RISCVRegisterBankInfo.cpp",
"RISCVAsmPrinter.cpp",
"RISCVCodeGenPrepare.cpp",
More information about the llvm-commits
mailing list