[llvm] 233b6ef - [RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 13:43:51 PDT 2023
Author: Philip Reames
Date: 2023-09-22T13:43:43-07:00
New Revision: 233b6ef66cc640bcde317fa2e2bfad78a52b257d
URL: https://github.com/llvm/llvm-project/commit/233b6ef66cc640bcde317fa2e2bfad78a52b257d
DIFF: https://github.com/llvm/llvm-project/commit/233b6ef66cc640bcde317fa2e2bfad78a52b257d.diff
LOG: [RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold
I'd guarded this case in D158874 to avoid regressions, and decided to go investigate what was going on. The solution turns out to be a generic splat matching extension to handle INSERT_SUBVECTOR. In theory, we could see these from other sources as well, but for some reason we only seem to see the i64 extract on rv32 case in practice. Not sure why that is to be honest.
Differential Revision: https://reviews.llvm.org/D159230
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 140473c595bbeb7..9a53c4a1297f500 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2961,6 +2961,11 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
}
static SDValue findVSplat(SDValue N) {
+ if (N.getOpcode() == ISD::INSERT_SUBVECTOR) {
+ if (!N.getOperand(0).isUndef())
+ return SDValue();
+ N = N.getOperand(1);
+ }
SDValue Splat = N;
if ((Splat.getOpcode() != RISCVISD::VMV_V_X_VL &&
Splat.getOpcode() != RISCVISD::VMV_S_X_VL) ||
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 000c7157fe8e827..8e6644821031c17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14429,10 +14429,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(N, 0);
// If VL is 1 and the scalar value won't benefit from immediate, we can
- // use vmv.s.x. Do this only if legal to avoid breaking i64 sext(i32)
- // patterns on rv32..
+ // use vmv.s.x.
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
- if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
+ if (isOneConstant(VL) &&
(!Const || Const->isZero() ||
!Const->getAPIntValue().sextOrTrunc(EltWidth).isSignedIntN(5)))
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index 9f70c2a18cb4977..53957586a8c629a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -897,31 +897,18 @@ define <1 x i64> @vrol_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
}
define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-RV32-LABEL: vrol_vx_v1i64:
-; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.v.x v9, a0
-; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v9, a0
-; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT: vand.vx v9, v9, a0
-; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
-; CHECK-RV32-NEXT: vor.vv v8, v10, v8
-; CHECK-RV32-NEXT: ret
-;
-; CHECK-RV64-LABEL: vrol_vx_v1i64:
-; CHECK-RV64: # %bb.0:
-; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.s.x v9, a0
-; CHECK-RV64-NEXT: li a0, 63
-; CHECK-RV64-NEXT: vand.vx v10, v9, a0
-; CHECK-RV64-NEXT: vsll.vv v10, v8, v10
-; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
-; CHECK-RV64-NEXT: vand.vx v9, v9, a0
-; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9
-; CHECK-RV64-NEXT: vor.vv v8, v10, v8
-; CHECK-RV64-NEXT: ret
+; CHECK-LABEL: vrol_vx_v1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: vand.vx v10, v9, a0
+; CHECK-NEXT: vsll.vv v10, v8, v10
+; CHECK-NEXT: vrsub.vi v9, v9, 0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vsrl.vv v8, v8, v9
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vrol_vx_v1i64:
; CHECK-ZVBB: # %bb.0:
@@ -1080,3 +1067,6 @@ define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
%x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
ret <8 x i64> %x
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-RV32: {{.*}}
+; CHECK-RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index cef10eefa2babae..8de463af78d6ff5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -1576,31 +1576,18 @@ define <1 x i64> @vror_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
}
define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-RV32-LABEL: vror_vx_v1i64:
-; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.v.x v9, a0
-; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v9, a0
-; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT: vand.vx v9, v9, a0
-; CHECK-RV32-NEXT: vsll.vv v8, v8, v9
-; CHECK-RV32-NEXT: vor.vv v8, v10, v8
-; CHECK-RV32-NEXT: ret
-;
-; CHECK-RV64-LABEL: vror_vx_v1i64:
-; CHECK-RV64: # %bb.0:
-; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.s.x v9, a0
-; CHECK-RV64-NEXT: li a0, 63
-; CHECK-RV64-NEXT: vand.vx v10, v9, a0
-; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10
-; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
-; CHECK-RV64-NEXT: vand.vx v9, v9, a0
-; CHECK-RV64-NEXT: vsll.vv v8, v8, v9
-; CHECK-RV64-NEXT: vor.vv v8, v10, v8
-; CHECK-RV64-NEXT: ret
+; CHECK-LABEL: vror_vx_v1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: vand.vx v10, v9, a0
+; CHECK-NEXT: vsrl.vv v10, v8, v10
+; CHECK-NEXT: vrsub.vi v9, v9, 0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vsll.vv v8, v8, v9
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vror_vx_v1i64:
; CHECK-ZVBB: # %bb.0:
@@ -1622,7 +1609,7 @@ define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vsll.vv v9, v8, v9
-; CHECK-RV32-NEXT: vmv.v.x v10, a0
+; CHECK-RV32-NEXT: vmv.s.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v8, v9
@@ -1655,7 +1642,7 @@ define <1 x i64> @vror_vi_rotl_v1i64(<1 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9
-; CHECK-RV32-NEXT: vmv.v.x v10, a0
+; CHECK-RV32-NEXT: vmv.s.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v8, v9
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