[llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)

[Simon Pilgrim via llvm-commits]

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@@ -2251,13 +2256,12 @@ SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
 }
 
 // Convert the promoted float value to the desired integer type
-SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteFloatOp_UnaryOp(SDNode *N, unsigned OpNo) {
   SDValue Op = GetPromotedFloat(N->getOperand(0));
   return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
 }
 
-SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N,
-                                                        unsigned OpNo) {
+SDValue DAGTypeLegalizer::PromoteFloatOp_BinOp(SDNode *N, unsigned OpNo) {
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RKSimon wrote:

This name is a little misleading, we normally expect both operands of a binop to be handled in a similar way.

https://github.com/llvm/llvm-project/pull/66924