[PATCH] D159073: [PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

[Esme Yi via Phabricator via llvm-commits]

Esme added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1108
+
+        MachineInstr *SrcMI = MRI->getVRegDef(TrueReg);
+        if (!SrcMI)
----------------
shchenz wrote:
> So we should guard this optimization before RA?
Yes, I do guard it by

```
 if (!TrueReg.isVirtual())
          break;
```


================
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1134
+          MaskSrc = 63 - SrcMI->getOperand(3).getImm();
+          MaskMI = llvm::countr_zero<uint64_t>(AndImm);
+        }
----------------
shchenz wrote:
> A follow up: is it possible to get result 0 for the ANDI if we know RLDICR clears more than andi masks, or for the ANDIS, if we know RLDICL leading 0 count is not smaller than 48? There should be other combinations... And if we are going to handle this case, maybe SHSrc does not need to be 0.
Good point!  In such scenarios we can eliminate ANDI_rec/ANDIS_rec instead of RLDICL/RLDICR and replace RLDICL/RLDICR with their record form RLDICL_rec/RLDICR_rec.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159073/new/

https://reviews.llvm.org/D159073