[llvm] 8a7f4ee - [llvm] Use llvm::is_contained (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 17:09:33 PDT 2023
Author: Kazu Hirata
Date: 2023-09-22T17:09:27-07:00
New Revision: 8a7f4eeb605324c8cb1996dba55ae3e24109d3d8
URL: https://github.com/llvm/llvm-project/commit/8a7f4eeb605324c8cb1996dba55ae3e24109d3d8
DIFF: https://github.com/llvm/llvm-project/commit/8a7f4eeb605324c8cb1996dba55ae3e24109d3d8.diff
LOG: [llvm] Use llvm::is_contained (NFC)
Added:
Modified:
llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
llvm/lib/Transforms/Scalar/SROA.cpp
Removed:
################################################################################
diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
index 410dd7fedad1a40..35816ea66cf9bc3 100644
--- a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
@@ -516,8 +516,7 @@ static RelaxAux initRelaxAux(LinkGraph &G) {
RelaxAux Aux;
Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32();
const auto &Features = G.getFeatures().getFeatures();
- Aux.Config.HasRVC =
- std::find(Features.begin(), Features.end(), "+c") != Features.end();
+ Aux.Config.HasRVC = llvm::is_contained(Features, "+c");
for (auto &S : G.sections()) {
if (!shouldRelax(S))
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index fbac23f63face6e..cc61373d51d7188 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1053,11 +1053,9 @@ bool AArch64ExpandPseudo::expandMultiVecPseudo(
auto ContiguousRange = ContiguousClass.getRegisters();
auto StridedRange = StridedClass.getRegisters();
unsigned Opc;
- if ((std::find(ContiguousRange.begin(), ContiguousRange.end(),
- Tuple.asMCReg()) != std::end(ContiguousRange))) {
+ if (llvm::is_contained(ContiguousRange, Tuple.asMCReg())) {
Opc = ContiguousOp;
- } else if ((std::find(StridedRange.begin(), StridedRange.end(),
- Tuple.asMCReg()) != std::end(StridedRange))) {
+ } else if (llvm::is_contained(StridedRange, Tuple.asMCReg())) {
Opc = StridedOpc;
} else
llvm_unreachable("Cannot expand Multi-Vector pseudo");
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 6a0e44b9c98a9b5..f60236080351a2c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1152,8 +1152,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
if (Pred.getSUnit()->getInstr()->getOpcode() != AMDGPU::V_PERM_B32_e64)
continue;
- if (Cand &&
- std::find(Counted.begin(), Counted.end(), Cand) != Counted.end())
+ if (Cand && llvm::is_contained(Counted, Cand))
break;
for (auto &Succ : Pred.getSUnit()->Succs) {
@@ -1174,7 +1173,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
}
Cand = VMEMLookup[MI];
- if (std::find(Counted.begin(), Counted.end(), Cand) != Counted.end()) {
+ if (llvm::is_contained(Counted, Cand)) {
MissedAny = true;
break;
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 47d28d5d0eab590..eaa4b2d40ebc28b 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -355,9 +355,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
- bool IsCalleeSaveSGPRSpill =
- std::find(CalleeSavedFIs.begin(), CalleeSavedFIs.end(), FI) !=
- CalleeSavedFIs.end();
+ bool IsCalleeSaveSGPRSpill = llvm::is_contained(CalleeSavedFIs, FI);
if (IsCalleeSaveSGPRSpill) {
// Spill callee-saved SGPRs into physical VGPR lanes.
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index 9612799e48337cc..9200b83efa3a84a 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -3126,8 +3126,7 @@ class llvm::sroa::AllocaSliceRewriter
if (IsDest) {
// Update the address component of linked dbg.assigns.
for (auto *DAI : at::getAssignmentMarkers(&II)) {
- if (any_of(DAI->location_ops(),
- [&](Value *V) { return V == II.getDest(); }) ||
+ if (llvm::is_contained(DAI->location_ops(), II.getDest()) ||
DAI->getAddress() == II.getDest())
DAI->replaceVariableLocationOp(II.getDest(), AdjustedPtr);
}
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