[llvm] [RISCV] Truncate constants to eltwidth before checking simm5 when con… (PR #67062)

[Philip Reames via llvm-commits]

================
@@ -14435,7 +14435,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     // patterns on rv32..
     ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
     if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
-        (!Const || Const->isZero() || !isInt<5>(Const->getSExtValue())))
+        (!Const || Const->isZero() ||
----------------
preames wrote:

Why is that SimplifyDemandedLowBitsHelper just above can't catch this case?  If only the low bits are demanded - which I think is what you're suggesting here - shouldn't that have folded the constant?

https://github.com/llvm/llvm-project/pull/67062