[llvm] [RISCV] Truncate constants to eltwidth before checking simm5 when con… (PR #67062)

[Philip Reames via llvm-commits]

================
@@ -14435,7 +14435,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     // patterns on rv32..
     ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
     if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
-        (!Const || Const->isZero() || !isInt<5>(Const->getSExtValue())))
+        (!Const || Const->isZero() ||
----------------
preames wrote:

That was the question I'd asked, but to reframe it, why not go ahead and convert the constant to the sign extended form eagerly?  Even if we don't convert to the vmv_s_x, isn't that a reasonable canonicalization of the vmv_v_x?  

p.s. I'm completely fine with this landing as is, just suggesting a potentially cleaner way of doing it.  

https://github.com/llvm/llvm-project/pull/67062