[llvm] 3b3ff5c - ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] (#67035)

[via llvm-commits]

Author: Ramkumar Ramachandra
Date: 2023-09-21T18:18:42+01:00
New Revision: 3b3ff5c1adae9198c19f950c81482255363a350c

URL: https://github.com/llvm/llvm-project/commit/3b3ff5c1adae9198c19f950c81482255363a350c
DIFF: https://github.com/llvm/llvm-project/commit/3b3ff5c1adae9198c19f950c81482255363a350c.diff

LOG: ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] (#67035)

70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced
VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the
core of this change is in TargetLowering. However, the commit
erroneously introduced dead code in RISCVISelLowering. Remove this dead
code.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d176fcaf54c2db0..8b745b2afaf956b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -715,8 +715,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT,
                          Legal);
 
-      setOperationAction({ISD::VP_FSHL, ISD::VP_FSHR}, VT, Expand);
-
       // Custom-lower extensions and truncations from/to mask types.
       setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
                          VT, Custom);