[llvm] [RISCV] Improve cleanup phase of RISCV Insert VSETVLI pass (PR #67144)

[Craig Topper via llvm-commits]

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@@ -1475,36 +1438,74 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
 
     if (!isVectorConfigInstr(MI)) {
       doUnion(Used, getDemanded(MI, MRI));
+      // We can't handle the case when the source AVL
+      // register of *NextMI is defined after MI
+      if (NextMI && NextMI->getOperand(1).isReg() && MI.getOperand(0).isReg() &&
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topperc wrote:

MI here can be any instruction right? What if it has more than 1 def?

https://github.com/llvm/llvm-project/pull/67144