[llvm] [AArch64][GlobalISel] Split offsets of consecutive stores to aid STP … (PR #66980)

[Pierre van Houtryve via llvm-commits]

================
@@ -492,7 +507,192 @@ bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
                      F.hasMinSize());
   AArch64PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, CSEInfo,
                                         RuleConfig, ST, MDT, LI);
-  return Impl.combineMachineInstrs();
+  bool Changed = Impl.combineMachineInstrs();
+
+  auto MIB = CSEMIRBuilder(MF);
+  MIB.setCSEInfo(CSEInfo);
+  Changed |= optimizeConsecutiveMemOpAddressing(MF, MIB);
----------------
Pierre-vh wrote:

Just wondering, do you need to do this because the combiner isn't powerful enough/is missing some feature to make this a normal rule (what feature?), or just because this is a separate transform that could technically be in another pass (but it's not worth creating a pass just for that)?

https://github.com/llvm/llvm-project/pull/66980