[llvm] ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (PR #66924)

[Ramkumar Ramachandra via llvm-commits]

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@@ -0,0 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x) {
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artagnon wrote:

No, SelectionDAG asserts because `vfcvt` wasn't designed for f16. If you look at `test/CodeGen/RISCV/half-intrinsics.ll`, you'll notice that [l]lrint are missing; so, I thought it would be reasonable not to support them in the vector variants as well.

https://github.com/llvm/llvm-project/pull/66924