[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Luke Lau via llvm-commits]

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@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
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lukel97 wrote:

Normally the m4 would already slide over the vmv.s.x here because we explicitly mark LMUL and VL as not demanded (we just check that VL has the same zero-ness). I think the reason as to why this the vsetvlis aren't being merged is because of the tail policy switch. 

[This old patch](https://reviews.llvm.org/D156319) that relaxed TA -> TU eliminates the toggle for this test (but it's overall not profitable for OoO processors): https://reviews.llvm.org/differential/changeset/?ref=4362822

For this specific test case though, should we not be doing this as a vmv.v.i with VL=1 anyway?

https://github.com/llvm/llvm-project/pull/66659