[llvm] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

[Craig Topper via llvm-commits]

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@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
 def FeatureStdExtZvknha
     : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
                        "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
-
-def FeatureStdExtZvknhb
-    : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
-                       "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
-                       [FeatureStdExtZvknha]>;
 def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
                                 AssemblerPredicate<(all_of FeatureStdExtZvknha),
                                 "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
 
+def FeatureStdExtZvknhb
+    : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+                       "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
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topperc wrote:

> If so, why should the check like this exist?
> 
> https://github.com/llvm/llvm-project/blob/69074bf144c1bf54040d289584e3d1d54f883a37/llvm/lib/Support/RISCVISAInfo.cpp#L935

That's a good question. That one is weird because Zve32x implies Zvl32b, but Zvl32b requires at least Zve32x. So they're mutually dependent.

https://github.com/llvm/llvm-project/pull/66860