[llvm] [AArch64][SVE2] Do not emit RSHRNB for large shifts (PR #66672)

[Matthew Devereau via llvm-commits]

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@@ -20241,6 +20241,10 @@ static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG,
     return SDValue();
   unsigned ShiftValue = SrlOp1->getZExtValue();
 
+  uint64_t EltSize = ResVT.getScalarSizeInBits();
+  if (ShiftValue > EltSize)
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MDevereau wrote:

Can you please explain why you both came to the conclusion that this isn't correct?

https://github.com/llvm/llvm-project/pull/66672